Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: In order to correctly perform error analysis, test, or the like, a 64B/66B converter of a PCS processing unit of a transmitter conforming to 10 GBASE-R PHY performs 64B/66B conversion on data on a block basis that is transmitted over four lanes, the block being formed of two columns. In the conversion, when a control signal inputted via a control signal input terminal indicates a normal operation mode, if an error code in a block to be converted is detected by an error detector, error expansion that replaces all 8 bytes of data in the block with an error code /E/ is performed. In contrast, when the control signal indicates an analysis mode, the error expansion is not performed even if an error code is detected by the error detector.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A communication system complying with SPI-4 Phase 2 standard includes a local device, an opposing device, a first data channel to transfer payload data from the local to the opposing device, a second data channel opposed to the first data channel, and a first status channel to be able to transfer data from the local to the opposing device. The local device periodically outputs buffer status information of a data buffer for storing payload data received over the second data channel to the first status channel. Further, the local device inserts the buffer status information between the payload data according to a priority of the buffer status information in order to output the buffer status information to the first data channel. The opposing device controls to output payload data to the second data channel according to the buffer status information received over the first status channel and the first data channel.

Abstract: In order to correctly perform error analysis, test, or the like, a 64B/66B converter of a PCS processing unit of a transmitter conforming to 10 GBASE-R PHY performs 64B/66B conversion on data on a block basis that is transmitted over four lanes, the block being formed of two columns. In the conversion, when a control signal inputted via a control signal input terminal indicates a normal operation mode, if an error code in a block to be converted is detected by an error detector, error expansion that replaces all 8 bytes of data in the block with an error code /E/ is performed. In contrast, when the control signal indicates an analysis mode, the error expansion is not performed even if an error code is detected by the error detector.

Abstract: A communication system complying with SPI-4 Phase 2 standard includes a local device, an opposing device, a first data channel to transfer payload data from the local to the opposing device, a second data channel opposed to the first data channel, and a first status channel to be able to transfer data from the local to the opposing device. The local device periodically outputs buffer status information of a data buffer for storing payload data received over the second data channel to the first status channel. Further, the local device inserts the buffer status information between the payload data according to a priority of the buffer status information in order to output the buffer status information to the first data channel. The opposing device controls to output payload data to the second data channel according to the buffer status information received over the first status channel and the first data channel.

Abstract: A function verification method comprises preparing a first function block that can execute the required functions in a semiconductor integrated circuit, preparing a second function block to be a verification target having a substantially identical configuration as the first function block and verifying functions of the second function block using the first function block.

Abstract: A function verification method comprises preparing a first function block that can execute the required functions in a semiconductor integrated circuit, preparing a second function block to be a verification target having a substantially identical configuration as the first function block and verifying functions of the second function block using the first function block.

Abstract: A communication system for transmitting/receiving data via a network line in frame, wherein the frame is transmitted/received using a first area in a preamble field of the frame as data to indicate the beginning of the frame, and a second area in the preamble field as a preamble information field having information.

Abstract: The present invention provides a driver circuitry having a single input terminal for receiving an input signal of binary digits consisting of high and low levels, and at least first and second output terminals, wherein the input signal is varied almost linearly in a first time period so as to be shifted between high and low levels, the driver circuitry comprises first and second control circuits. The first control circuit is coupled to the input terminal for receiving the input signal. The first control circuit is also coupled to the first output terminal for outputting a first output signal of binary digits via the first output terminal. The first control circuit is biased between a high voltage line which supplies a high level of voltage and a low voltage line which supplies a low level of voltage.