Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: An electronic circuit includes: first circuits each including a first FET having a source supplied with at least one of a first voltage and a second voltage; and a second circuits each of which is associated with a respective one of the first circuits, and generates a back bias voltage applied to the first FET so as to change in accordance with a change of at least one of the first and second voltages.

Abstract: An electronic circuit includes: first circuits each including a first FET having a source supplied with at least one of a first voltage and a second voltage; and a second circuits each of which is associated with a respective one of the first circuits, and generates a back bias voltage applied to the first FET so as to change in accordance with a change of at least one of the first and second voltages.

Abstract: In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: A timing analysis method evaluates a performance of a target circuit that is to be designed, and includes calculating a correlation coefficient r between two arbitrary macro cells that are coupled and form the target circuit based on layout information including an arrangement of macro cells forming the target circuit and correlation information indicating a correlation between two macro cells that are coupled for each of arrangements of macro cell pairs, calculating a distribution function ? of a standard deviation of delay times of the two arbitrary macro cells based on the correlation coefficient ?, and carrying out a statistical timing analysis of the target circuit based on the correlation coefficient r and the distribution function ? of the standard deviation with respect to each of the macro cell pairs forming the target circuit.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: A timing analysis method evaluates a performance of a target circuit that is to be designed, and includes calculating a correlation coefficient r between two arbitrary macro cells that are coupled and form the target circuit based on layout information including an arrangement of macro cells forming the target circuit and correlation information indicating a correlation between two macro cells that are coupled for each of arrangements of macro cell pairs, calculating a distribution function ? of a standard deviation of delay times of the two arbitrary macro cells based on the correlation coefficient ?, and carrying out a statistical timing analysis of the target circuit based on the correlation coefficient r and the distribution function ? of the standard deviation with respect to each of the macro cell pairs forming the target circuit.

Abstract: In gates, a gate length is same as that of an isolated Poly on a layout, however, is different from that of the isolated Poly on an actual silicon wafer. When the distance between the gates that is spacing between the gate becomes larger to some degree, the proximity effect is lost and the proximity Poly becomes same as the isolated Poly. In this way, because the correlation with another macro-cell arranged adjacent differs when the distance between the gates differs, the correlation coefficient varies. Therefore, correlation is grouped according to the distance between the gates.

Abstract: A semiconductor memory device including a write control system for controlling data write to a selected memory cell on the basis of a write control signal, an external terminal for test, a write pulse generating circuit for generating a test write pulse on the basis of a set signal given from the external terminal and the write control signal, and supplying it to the write control system. The write pulse generating circuit includes a pulse-width changing circuit for variably setting a pulse width of the test write pulse on the basis of the set signal. The test write pulse width can be freely and precisely set by using the minimum possible number of external terminals for test. A test write pulse width which agrees with the real capacity of high speed devices can be obtained even by using relatively economical, low speed testing equipment.

Abstract: A bipolar-transistor type semiconductor memory device including a normal memory cell array, redundancy memory cell array, a redundancy driving circuit, and a redundancy address decision circuit. When the redundancy address decision circuit determines that the input address coincides with the address of a defective circuit portion, the redundancy driving circuit is driven to enable the redundancy memory cell array instead of the normal memory cell array.