Patents by Inventor Tomohide Jokan

Tomohide Jokan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9116741
    Abstract: According to an embodiment, a computer program product includes a computer-readable medium including program, when executed by a computer, to have a plurality of modules run by the computer. The computer includes a memory having a shared area, which is an area accessible to only those modules which run cooperatively and storing therein execution module identifiers. Each of the modules includes a first operation configured to store, just prior to a switchover of operations to an other module that runs cooperatively, an identifier of the other module as the execution module identifier in the shared area; and a second operation configured to execute, when the execution module identifier stored in the shared area matches with an identifier of own module immediately after a switchover of operations from the other module, a function inside the own module.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: August 25, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyoshi Haruki, Mikio Hashimoto, Fukutomo Nakanishi, Ryotaro Hayashi, Yurie Fujimatsu, Tomohide Jokan, Takeshi Kawabata
  • Patent number: 8732480
    Abstract: According to an embodiment, a memory management device increments a lower value of a first counter, updates the counter by incrementing an upper value and resetting the lower value when the lower value overflows, increments to update the lower counter value when the upper value is incremented as a result of writing a second data piece having the upper value in common to a memory, recalculates a first secret value calculated using the first counter values and a root secret value in response to the first counter update, writes a first data piece and the first secret value to the memory, and at reading of the first data piece and the first secret value, calculates a second secret value using the updated first counter values and the root secret value, and compares the first secret value with the second secret value to verify the first data piece.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mikio Hashimoto, Hiroyoshi Haruki, Takeshi Kawabata, Tomohide Jokan, Yurie Fujimatsu, Ryotaro Hayashi, Fukutomo Nakanishi
  • Publication number: 20130219408
    Abstract: According to an embodiment, a computer program product includes a computer-readable medium including program, when executed by a computer, to have a plurality of modules run by the computer. The computer includes a memory having a shared area, which is an area accessible to only those modules which run cooperatively and storing therein execution module identifiers. Each of the modules includes a first operation configured to store, just prior to a switchover of operations to an other module that runs cooperatively, an identifier of the other module as the execution module identifier in the shared area; and a second operation configured to execute, when the execution module identifier stored in the shared area matches with an identifier of own module immediately after a switchover of operations from the other module, a function inside the own module.
    Type: Application
    Filed: August 15, 2012
    Publication date: August 22, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyoshi HARUKI, Mikio HASHIMOTO, Fukutomo NAKANISHI, Ryotaro HAYASHI, Yurie FUJIMATSU, Tomohide JOKAN, Takeshi KAWABATA
  • Patent number: 8219767
    Abstract: A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: July 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Hiroshi Yao, Tomohide Jokan, Tatsunori Kanai
  • Publication number: 20120079283
    Abstract: According to an embodiment, a memory management device increments a lower value of a first counter, updates the counter by incrementing an upper value and resetting the lower value when the lower value overflows, increments to update the lower counter value when the upper value is incremented as a result of writing a second data piece having the upper value in common to a memory, recalculates a first secret value calculated using the first counter values and a root secret value in response to the first counter update, writes a first data piece and the first secret value to the memory, and at reading of the first data piece and the first secret value, calculates a second secret value using the updated first counter values and the root secret value, and compares the first secret value with the second secret value to verify the first data piece.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mikio HASHIMOTO, Hiroyoshi HARUKI, Takeshi KAWABATA, Tomohide JOKAN, Yurie FUJIMATSU, Ryotaro HAYASHI, Fukutomo NAKANISHI
  • Patent number: 7971014
    Abstract: In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a backup memory unit that is non-volatile. Further, according to the data and the write destination address extracted from the backup data, the data is written to a storage area of the main-memory unit indicated by the write destination address.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Hiroshi Yao, Tomohide Jokan, Tatsunori Kanai
  • Publication number: 20090172325
    Abstract: In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a backup memory unit that is non-volatile. Further, according to the data and the write destination address extracted from the backup data, the data is written to a storage area of the main-memory unit indicated by the write destination address.
    Type: Application
    Filed: August 26, 2008
    Publication date: July 2, 2009
    Inventors: Kenichiro YOSHII, Hiroshi YAO, Tomohide JOKAN, Tatsunori KANAI
  • Publication number: 20090164743
    Abstract: A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address.
    Type: Application
    Filed: August 27, 2008
    Publication date: June 25, 2009
    Inventors: Kenichiro YOSHII, Hiroshi Yao, Tomohide Jokan, Tatsunori Kanai