Abstract: It is an object to provide a technique useful for embryo transfer and development of reproductive medical care. Provided are a sperm activator containing a disrupted product of one or more cells selected from the group consisting of adipose tissue-derived stem cells, dental pulp-derived stem cells, bone marrow-derived stem cells, and umbilical cord blood-derived stem cells as an active ingredient, and an artificial insemination method utilizing the same.

Abstract: It is an object to provide a technique useful for embryo transfer and development of reproductive medical care. Provided are a sperm activator containing a disrupted product of one or more cells selected from the group consisting of adipose tissue-derived stem cells, dental pulp-derived stem cells, bone marrow-derived stem cells, and umbilical cord blood-derived stem cells as an active ingredient, and an artificial insemination method utilizing the same.

Abstract: A pitch conversion device and pitch conversion method is directed to convert the pitch of a plurality of partition members arranged parallel to each other along an X-direction and include a plurality of entry members arranged parallel to each other in the X-direction and configured to enter between neighboring partition members, and a pushing member to push the plurality of entry members in turn and allow them to enter neighboring partition members while moving in the X direction. The entry members are biased in an exiting direction from between the neighboring partition members.

Abstract: A pitch conversion device and pitch conversion method is directed to convert the pitch of a plurality of partition members arranged parallel to each other along an X-direction and include a plurality of entry members arranged parallel to each other in the X-direction and configured to enter between neighboring partition members, and a pushing member to push the plurality of entry members in turn and allow them to enter neighboring partition members while moving in the X direction. The entry members are biased in an exiting direction from between the neighboring partition members.

Abstract: An ESD analysis method and computer program product are disclosed. A circuit simulation is executed of design data of a semiconductor integrated circuit including a first power supply pad, a second power supply pad and a plurality of current paths between the first power supply pad and the second power supply pad, to calculate potentials in the plurality of current paths, when one of an ESD current and an ESD voltage is applied between the first power supply pad and the second power supply pad. An ESD tolerance is checked by calculating a potential difference between a first node coupled to the first power supply pad and a second node coupled to the second power supply pad, based on the calculated potentials. The first node and the second node are determined as nodes to be coupled to a border cell upon the potential difference being lower than a predetermined value.

Abstract: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.

Abstract: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.

Abstract: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.

Abstract: A baud rate detector detects baud rate of received serial data based on an AT command included in the serial data. A character discriminator detects parity type and data format of the serial data based on the AT command in the serial data. An information relay 16 sets the baud rate, the parity type and the data format to a register in a UART (Universal Asynchronous Receiver-Transmitter). A clock generator generates a clock signal for data reception and supplies the clock signal to the UART.