Patents by Inventor Tomohiro Okamura
Tomohiro Okamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230025401Abstract: A hollow fiber membrane module includes a pressure vessel, a plurality of hollow fiber membrane elements arranged in series inside the pressure vessel, and a connector that connects the hollow fiber membrane elements to each other. Each of the hollow fiber membrane elements includes a plurality of hollow fiber membranes, and a double-core tube extending in a longitudinal direction of the plurality of hollow fiber membrane elements. The connector includes a first channel and a second channel that do not communicate with each other. Between the hollow fiber membrane elements, the outer channels of the hollow fiber membrane elements are connected to each other through the first channel, the inner channels of the hollow fiber membrane elements are connected to each other through the second channel, and hollow portions of the hollow fiber membranes communicate with the inner channels through the second channel.Type: ApplicationFiled: December 17, 2020Publication date: January 26, 2023Applicant: TOYOBO CO., LTD.Inventors: Tomohiro Okamura, Hiroyuki Yoshida, Hideki Mihara, Mikio Katsube
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Patent number: 11331630Abstract: A hollow fiber membrane module includes one pressure vessel, and at least one hollow fiber membrane element loaded in the pressure vessel. Each of the element includes a plurality of hollow fiber membranes each having openings at both ends, a bypass tube, and a supply port and a discharge port provided on one end side in a longitudinal direction. The supply port is in communication with inflow-side openings of hollow fiber membranes. The bypass tube is provided in the longitudinal direction of the element, has an inflow port at an end portion on a side of outflow-side openings of the hollow fiber membranes, and has an outflow port at an end portion on a side of the inflow-side openings of the hollow fiber membranes. The outflow-side openings of hollow fiber membranes are in communication with the inflow port, and the outflow port is in communication with the discharge port.Type: GrantFiled: June 20, 2018Date of Patent: May 17, 2022Assignee: TOYOBO CO., LTD.Inventors: Mikio Katsube, Hideto Kotera, Tomohiro Okamura, Hidehiko Sakurai
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Publication number: 20210069649Abstract: A hollow fiber membrane module includes one pressure vessel, and at least one hollow fiber membrane element loaded in the pressure vessel. Each of the element includes a plurality of hollow fiber membranes each having openings at both ends, a bypass tube, and a supply port and a discharge port provided on one end side in a longitudinal direction. The supply port is in communication with inflow-side openings of hollow fiber membranes. The bypass tube is provided in the longitudinal direction of the element, has an inflow port at an end portion on a side of outflow-side openings of the hollow fiber membranes, and has an outflow port at an end portion on a side of the inflow-side openings of the hollow fiber membranes. The outflow-side openings of hollow fiber membranes are in communication with the inflow port, and the outflow port is in communication with the discharge port.Type: ApplicationFiled: June 20, 2018Publication date: March 11, 2021Applicant: Toyobo Co., Ltd.Inventors: Mikio KATSUBE, Hideto KOTERA, Tomohiro OKAMURA, Hidehiko SAKURAI
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Patent number: 9702444Abstract: A method for manufacturing a fluid power transmission includes a first step of assembling a blade/core provisional assembly having a plurality of blades movably linked to a core, involving aligning the plurality of blades on a blade alignment jig, laying the core over a group of blades while extending a projecting piece provided on each blade through a latching hole provided in the core, and bending an extremity part of the projecting piece thus preventing the projecting piece from coming out of the latching hole, a second step of setting the blade/core provisional assembly at a predetermined position on an inside face of the shell, and a third step of carrying out brazing between the projecting piece and the latching hole and between the blade and the shell. Such method provides a high quality impeller of a fluid power transmission by joining a shell, a blade, and a core.Type: GrantFiled: April 23, 2013Date of Patent: July 11, 2017Assignee: Yutaka Giken Co., Ltd.Inventors: Tomohiro Okamura, Katsuyoshi Aoshima, Masaru Nambara, Nobutaka Amma, Yuji Horie
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Publication number: 20150128418Abstract: A method for manufacturing a fluid power transmission includes a first step of assembling a blade/core provisional assembly having a plurality of blades movably linked to a core, involving aligning the plurality of blades on a blade alignment jig, laying the core over a group of blades while extending a projecting piece provided on each blade through a latching hole provided in the core, and bending an extremity part of the projecting piece thus preventing the projecting piece from coming out of the latching hole, a second step of setting the blade/core provisional assembly at a predetermined position on an inside face of the shell, and a third step of carrying out brazing between the projecting piece and the latching hole and between the blade and the shell. Such method provides a high quality impeller of a fluid power transmission by joining a shell, a blade, and a core.Type: ApplicationFiled: April 23, 2013Publication date: May 14, 2015Inventors: Tomohiro Okamura, Katsuyoshi Aoshima, Masaru Nambara, Nobutaka Amma, Yuji Horie
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Patent number: 8071415Abstract: There is provided a method of fabricating a semiconductor device having plural light receiving elements, and having an amplifying element, the method including: a) forming an active region on the semiconductor substrate for configuring the amplifying element; b) forming a light receiving element region on the semiconductor substrate for forming the plural light receiving elements, with the active region acting as a reference for positioning; c) implanting an impurity into the light receiving element region; d) repeating the process b) and the process c) a number of times that equals a number of diffusion layers in the light receiving element region; e) after implanting the impurity, performing a drive-in process to carry out drive in of the semiconductor substrate; and f) the process e), forming an amplifying element forming process by implanting an impurity in the active region.Type: GrantFiled: March 15, 2010Date of Patent: December 6, 2011Assignee: Lapis Semiconductor Co., Ltd.Inventors: Tomohiro Okamura, Masao Okihara
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Publication number: 20110117741Abstract: There is provided a method of fabricating an SOI wafer, the method including: a) preparing a bonded SOI substrate that has a buried oxide layer and an SOI layer formed in this sequence on a circular plate shaped support, and at a peripheral edge portion of the support substrate, has a silicon island region in which the SOI layer is not well formed with scattered defective silicon layer; b) etching a silicon island region defective silicon layer to remove the defective silicon layer scattered in the silicon island region by dry etching; and c) etching a silicon island region buried oxide layer to remove the buried oxide layer in the silicon island region by wet etching.Type: ApplicationFiled: October 27, 2010Publication date: May 19, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventors: Tomohiro Okamura, Masao Okihara
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Publication number: 20100248410Abstract: There is provided a method of fabricating a semiconductor device having plural light receiving elements, and having an amplifying element, the method including: a) forming an active region on the semiconductor substrate for configuring the amplifying element; b) forming a light receiving element region on the semiconductor substrate for forming the plural light receiving elements, with the active region acting as a reference for positioning; c) implanting an impurity into the light receiving element region; d) repeating the process b) and the process c) a number of times that equals a number of diffusion layers in the light receiving element region; e) after implanting the impurity, performing a drive-in process to carry out drive in of the semiconductor substrate; and f) the process e), forming an amplifying element forming process by implanting an impurity in the active region.Type: ApplicationFiled: March 15, 2010Publication date: September 30, 2010Applicant: OKI SEMICONDUCTOR CO., LTD.Inventors: Tomohiro Okamura, Masao Okihara
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Patent number: 7790568Abstract: A method for fabricating a semiconductor device includes: providing a semiconductor substrate; forming a STI region on the semiconductor substrate; forming a channel region on the semiconductor substrate; implanting impurities into the STI region; and performing a thermal treatment to diffuse impurities to a side of the channel region.Type: GrantFiled: August 29, 2006Date of Patent: September 7, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Tomohiro Okamura
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Publication number: 20080057668Abstract: According to the present invention, a method for fabricating a semiconductor device includes: providing a semiconductor substrate; forming a STI region on the semiconductor substrate; forming a channel region on the semiconductor substrate; implanting impurities into the STI region; and performing a thermal treatment to diffuse impurities to a side of the channel region.Type: ApplicationFiled: August 29, 2006Publication date: March 6, 2008Inventor: Tomohiro Okamura
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Patent number: 7141458Abstract: A method of manufacturing a semiconductor device includes a step of forming a device region 5 that is separated by a device-separation insulating film 4 formed in a part of an SOI layer, a step of forming a gate insulating film 6a on a device region 5 so that the device region 5 can be exposed on both sides of the gate insulating film 6a, a step of forming a gate electrode 7a with polysilicon on the gate insulating film 6a, a step of adjusting the area of exposed silicon so that the area of exposed silicon can be a prescribed area by forming at least either a pseudo region 5b or a pseudo electrode 7b to control the growth rate in growing an epitaxial layer 9, and a step of conducting low-temperature epitaxial growth of silicon.Type: GrantFiled: January 26, 2005Date of Patent: November 28, 2006Assignee: Oki Electric Industry Co., Ltd.Inventor: Tomohiro Okamura
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Patent number: 7118978Abstract: A method for producing a semiconductor device with an SOI substrate having a support substrate 1 and a semiconductor layer 3 that interpose a first insulating film 2 between them includes the following steps. An element region and an element-separation region 4 are formed in the semiconductor layer 3. A gate insulating film 5 is formed on the semiconductor layer 3. A gate electrode 6 is formed on the gate insulating film 5. A second insulating film 7 is formed. The gate insulating film 5 is removed. First thickness adjustment is performed. Ion implantation introducing low concentration impurities is performed on the thickness-adjusted semiconductor layers 3 and 8. A first sidewall portion 7a is formed on the side surfaces of the gate electrode 6. A second sidewall portion 10a is formed on the side surfaces of the first sidewall portion 7a.Type: GrantFiled: November 16, 2004Date of Patent: October 10, 2006Assignee: Oki Electric Industry Co., Ltd.Inventor: Tomohiro Okamura
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Publication number: 20050260805Abstract: A method for producing a semiconductor device with an SOI substrate having a support substrate 1 and a semiconductor layer 3 that interpose a first insulating film 2 between them includes the following steps. An element region and an element-separation region 4 are formed in the semiconductor layer 3. A gate insulating film 5 is formed on the semiconductor layer 3. A gate electrode 6 is formed on the gate insulating film 5. A second insulating film 7 is formed. The gate insulating film 5 is removed. First thickness adjustment is performed. Ion implantation introducing low concentration impurities is performed on the thickness-adjusted semiconductor layers 3 and 8. A first sidewall portion 7a is formed on the side surfaces of the gate electrode 6. A second sidewall portion 10a is formed on the side surfaces of the first sidewall portion 7a.Type: ApplicationFiled: November 16, 2004Publication date: November 24, 2005Applicant: Oki Electric Co., Ltd.Inventor: Tomohiro Okamura
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Publication number: 20050189590Abstract: A method of manufacturing a semiconductor device includes a step of forming a device region 5 that is separated by a device-separation insulating film 4 formed in a part of an SOI layer, a step of forming a gate insulating film 6a on a device region 5 so that the device region 5 can be exposed on both sides of the gate insulating film 6a, a step of forming a gate electrode 7a with polysilicon on the gate insulating film 6a, a step of adjusting the area of exposed silicon so that the area of exposed silicon can be a prescribed area by forming at least either a pseudo region 5b or a pseudo electrode 7b to control the growth rate in growing an epitaxial layer 9, and a step of conducting low-temperature epitaxial growth of silicon.Type: ApplicationFiled: January 26, 2005Publication date: September 1, 2005Applicant: Oki Electric Industry Co., Ltd.Inventor: Tomohiro Okamura