Patents by Inventor Tomohisa Kitano

Tomohisa Kitano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6291311
    Abstract: On the surface of a field oxide film (3 of FIG. 2e) formed-on a substrate region where the effective thickness in the vertical direction of a substrate is diminished due to the presence of a crystal defect (2 of FIG. 1a), the field oxide film is etched by a predetermined thickness until a recess (4 of FIG. 2f) ascribable to the presence of the defect is exposed (step of FIG. 2f). A new oxide film then is formed in an amount corresponding to the above-mentioned thickness on the field oxide film (step of FIG. 3g) to diminish the depth of the recess ascribable to the presence of the defect. To provide a semiconductor device in which leakage between elements can be eliminated with a thin LOCOS oxide film thickness remaining unchanged.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: September 18, 2001
    Assignee: NEC Corporation
    Inventors: Takuo Ohashi, Tomohisa Kitano
  • Publication number: 20010015466
    Abstract: On the surface of a field oxide film (3 of FIG. 2e) formed on a substrate region where the effective thickness in the vertical direction of a substrate is diminished due to the presence of a crystal defect (2 of FIG. 1a), the field oxide film is etched by a predetermined thickness until a recess (4 of FIG. 2f) ascribable to the presence of the defect is exposed (step of FIG. 2f). A new oxide film then is formed in an amount corresponding to the above-mentioned thickness on the field oxide film (step of FIG. 3g) to diminish the depth of the recess ascribable to the presence of the defect. To provide a semiconductor device in which leakage between elements can be eliminated with a thin LOCOS oxide film thickness remaining unchanged.
    Type: Application
    Filed: January 19, 2001
    Publication date: August 23, 2001
    Inventors: Takuo Ohashi, Tomohisa Kitano
  • Publication number: 20010008297
    Abstract: On the surface of a field oxide film (3 of FIG. 2e) formed on a substrate region where the effective thickness in the vertical direction of a substrate is diminished due to the presence of a crystal defect (2 of FIG. 1a), the field oxide film is etched by a predetermined thickness until a recess (4 of FIG. 2f) ascribable to the presence of the defect is exposed (step of FIG. 2f). A new oxide film then is formed in an amount corresponding to the above-mentioned thickness on the field oxide film (step of FIG. 3g) to diminish the depth of the recess ascribable to the presence of the defect. To provide a semiconductor device in which leakage between elements can be eliminated with a thin LOCOS oxide film thickness remaining unchanged.
    Type: Application
    Filed: January 19, 2001
    Publication date: July 19, 2001
    Inventors: Takuo Ohashi, Tomohisa Kitano
  • Publication number: 20010001500
    Abstract: On the surface of a field oxide film (3 of FIG. 2e) formed on a substrate region where the effective thickness in the vertical direction of a substrate is diminished due to the presence of a crystal defect (2 of FIG. 1a), the field oxide film is etched by a predetermined thickness until a recess (4 of FIG. 2f) ascribable to the presence of the defect is exposed (step of FIG. 2f). A new oxide film then is formed in an amount corresponding to the above-mentioned thickness on the field oxide film (step of FIG. 3g) to diminish the depth of the recess ascribable to the presence of the defect. To provide a semiconductor device in which leakage between elements can be eliminated with a thin LOCOS oxide film thickness remaining unchanged.
    Type: Application
    Filed: January 19, 2001
    Publication date: May 24, 2001
    Inventors: Takuo Ohashi, Tomohisa Kitano
  • Patent number: 6214700
    Abstract: On the surface of a field oxide film (3 of FIG. 2e) formed on a substrate region where the effective thickness in the vertical direction of a substrate is diminished due to the presence of a crystal defect (2 of FIG. 1a), the field oxide film is etched by a predetermined thickness until a recess (4 of FIG. 2f) ascribable to the presence of the defect is exposed (step of FIG. 2f). A new oxide film then is formed in an amount corresponding to the above-mentioned thickness on the field oxide film (step of FIG. 3g) to diminish the depth of the recess ascribable to the presence of the defect. To provide a semiconductor device in which leakage between elements can be eliminated with a thin LOCOS oxide film thickness remaining unchanged.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: April 10, 2001
    Assignee: NEC Corporation
    Inventors: Takuo Ohashi, Tomohisa Kitano
  • Patent number: 6057215
    Abstract: In a process for manufacturing a semiconductor device, an N-well, a field oxide film, a gate oxide film and a polysilicon gate electrode are formed on a P-type silicon substrate. Arsenic is ion-implanted into the substrate using the polysilicon gate electrode as a mask, to form N-type diffused source/drain regions. Boron fluoride is ion-implanted into the N-well using the polysilicon gate electrode as a mask, to form P-type diffused source/drain regions. A titanium film is deposited on the whole surface, and a first heat treatment is carried out at a first temperature to form titanium silicide. Metal titanium remaining on the titanium silicide is removed so as to selectively form titanium silicide on the polysilicon gate electrode, the N-type diffused source/drain regions and the P-type diffused source/drain regions. A second heat treatment is carried out on the refractory metal silicide at a second temperature higher than the first temperature.
    Type: Grant
    Filed: May 31, 1996
    Date of Patent: May 2, 2000
    Assignee: NEC Corporation
    Inventor: Tomohisa Kitano
  • Patent number: 5779797
    Abstract: A wafer boat having a structure for supporting a plurality of wafers one above another at an interval. The structure includes a plurality of support posts disposed upright and essentially perpendicular to principal surfaces of the wafers at positions around the wafers, and a plurality of supporting bars each of which extends laterally from each of the support posts and supports a wafer back at positions thereof spaced apart from a center of the wafer by a distance corresponding to two-thirds of the radius of the wafer. The wafers may be (001)-wafers, and the supporting bars may support the wafer back at positions thereof corresponding to ?100! or ?110! crystal orientation. The arrangement enables the reduction of the stress generated due to the weight of the wafer.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: July 14, 1998
    Assignee: NEC Corporation
    Inventor: Tomohisa Kitano
  • Patent number: 5665646
    Abstract: In order to retrain from rising a temperature of a phase transition for a silicide of refractory metal, such as Ti, Co, Pt, Ni, Mo, W, Ta, or the like, a method for manufacturing a semiconductor device has a process of forming a low electric resistance layer on a surface of a silicon. The process comprises a step of forming, on the surface of the silicon, a layer of silicide of refractory metal with phase transition nuclei therein. The process further comprises a step of subjecting the silicide to phase transition by a phase transition heat treatment at a predetermined transition temperature to convert the silicide layer into a crystalline phase which has low electric resistance. Thereby the low electric resistance layer is formed. Preferably, the silicide of refractory metal with phase transition nuclei is amorphous or the silicide of refractory metal with phase transition nuclei is crystalline but has damages.
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: September 9, 1997
    Assignee: NEC Corporation
    Inventor: Tomohisa Kitano
  • Patent number: 5353324
    Abstract: A method for detecting and evaluating crystal defects existing in the extreme neighborhood of the surface of a crystal specimen through the use of X-ray analyzing micrography. Synchrotron radiation is used as the X-ray source. A monochromatic X-ray beam generated from the synchrotron radiation is directed into the crystal specimen at a glancing angle smaller than the critical angle of said crystal specimen relative to said monochromatic X-ray beam. The diffracted X-rays from the crystal specimen due to asymmetrical reflection are detected in order to observe the resulting diffracted image.
    Type: Grant
    Filed: April 8, 1992
    Date of Patent: October 4, 1994
    Assignee: NEC Corporation
    Inventor: Tomohisa Kitano