Patents by Inventor Tomohisa Mizuno
Tomohisa Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977099Abstract: A method for manufacturing a semiconductor device in which probes and the layout of the electrode pads of a test element group (TEG) are associated is provided. As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Thus, it is necessary to associate the probes and the layout of the electrode pad. According to the method, a layout of a TEG electrode pad corresponding to a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology is provided.Type: GrantFiled: February 6, 2018Date of Patent: May 7, 2024Assignee: Hitachi High-Tech CorporationInventors: Tomohisa Ohtaki, Takayuki Mizuno, Ryo Hirano, Toru Fujimura, Shigehiko Kato, Yasuhiko Nara, Katsuo Ohki, Akira Kageyama, Masaaki Komori
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Patent number: 8941092Abstract: Disclosed are a method which improves the performance of a semiconductor element, and a semiconductor element with improved performance. The method for forming a semiconductor element structure includes a heterojunction forming step in which a heterojunction is formed between a strained semiconductor layer (21) in which a strained state is maintained, and relaxed semiconductor layers (23, 25). The heterojunction is formed by performing ion implantation from the surface of a substrate (50) which has a strained semiconductor layer (20) partially covered with a covering layer (30) on an insulating oxide film (40), and altering the strained semiconductor layer (20) where there is no shielding from the covering layer (30) to relaxed semiconductor layers (23, 25) by relaxing the strained state of the strained semiconductor layer (20), while maintaining the strained state of the strained semiconductor layer (21) where there is shielding from the covering layer (30).Type: GrantFiled: March 5, 2012Date of Patent: January 27, 2015Assignee: Kanagawa UniversityInventor: Tomohisa Mizuno
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Publication number: 20120168818Abstract: Disclosed are a method which improves the performance of a semiconductor element, and a semiconductor element with improved performance. The method for forming a semiconductor element structure includes a heterojunction forming step in which a heterojunction is formed between a strained semiconductor layer (21) in which a strained state is maintained, and relaxed semiconductor layers (23, 25). The heterojunction is formed by performing ion implantation from the surface of a substrate (50) which has a strained semiconductor layer (20) partially covered with a covering layer (30) on an insulating oxide film (40), and altering the strained semiconductor layer (20) where there is no shielding from the covering layer (30) to relaxed semiconductor layers (23, 25) by relaxing the strained state of the strained semiconductor layer (20), while maintaining the strained state of the strained semiconductor layer (21) where there is shielding from the covering layer (30).Type: ApplicationFiled: March 5, 2012Publication date: July 5, 2012Applicant: KANAGAWA UNIVERSITYInventor: Tomohisa Mizuno
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Patent number: 7659537Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y?0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.Type: GrantFiled: January 23, 2006Date of Patent: February 9, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Shinichi Takagi, Tomohisa Mizuno
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Publication number: 20070187669Abstract: A field effect transistor fabricated in a device isolation region includes a Si1-xGex layer (0<x?1) that a lattice strain is relaxed, a strained Si layer formed on the Si1-xGex, a gate electrode insulatively disposed over a part of the strained Si layer, source and drain regions formed in the strained Si layer with the gate electrode being arranged between the source and drain regions; and a Si film covering side walls of the Si1-xGex layer on ends of the device isolation region.Type: ApplicationFiled: April 13, 2007Publication date: August 16, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Tomohisa Mizuno, Koji Usuda
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Publication number: 20060118776Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y?0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.Type: ApplicationFiled: January 23, 2006Publication date: June 8, 2006Inventors: Tsutomu Tezuka, Shinichi Takagi, Tomohisa Mizuno
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Patent number: 7009200Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y?0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.Type: GrantFiled: July 1, 2003Date of Patent: March 7, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Shinichi Takagi, Tomohisa Mizuno
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Publication number: 20050194585Abstract: A field effect transistor fabricated in a device isolation region includes a Si1-xGex layer (0<x?1) that a lattice strain is relaxed, a strained Si layer formed on the Si1-xGex, a gate electrode insulatively disposed over a part of the strained Si layer, source and drain regions formed in the strained Si layer with the gate electrode being arranged between the source and drain regions; and a Si film covering side walls of the Si1-xGex layer on ends of the device isolation region.Type: ApplicationFiled: March 3, 2005Publication date: September 8, 2005Inventors: Tsutomu Tezuka, Tomohisa Mizuno, Koji Usuda
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Patent number: 6917096Abstract: A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.Type: GrantFiled: July 2, 2003Date of Patent: July 12, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Atsushi Kurobe, Tsutomu Tezuka, Tomohisa Mizuno, Shinichi Takagi
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Publication number: 20040155256Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y≧0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.Type: ApplicationFiled: July 1, 2003Publication date: August 12, 2004Inventors: Tsutomu Tezuka, Shinichi Takagi, Tomohisa Mizuno
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Patent number: 6774390Abstract: A semiconductor device includes an insulating layer, a semiconductor board formed on a selected portion of the insulating layer, a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, which is different from the semiconductor board in lattice constant, and having source and drain regions and a channel region therebetween, the area of the channel region being larger than that of the bottom surface of the semiconductor board, which contacts the insulating layer, and a gate electrode formed on the channel region via a gate insulating layer.Type: GrantFiled: February 21, 2003Date of Patent: August 10, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Tsutomu Tezuka, Tomohisa Mizuno, Shinichi Takagi
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Publication number: 20040070051Abstract: A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.Type: ApplicationFiled: July 2, 2003Publication date: April 15, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoharu Sugiyama, Atsushi Kurobe, Tsutomu Tezuka, Tomohisa Mizuno, Shinichi Takagi
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Patent number: 6709909Abstract: A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.Type: GrantFiled: May 19, 2003Date of Patent: March 23, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Tomohisa Mizuno, Naoharu Sugiyama, Shinichi Takagi
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Publication number: 20030227036Abstract: A semiconductor device includes an insulating layer, a semiconductor board formed on a selected portion of the insulating layer, a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, which is different from the semiconductor board in lattice constant, and having source and drain regions and a channel region therebetween, the area of the channel region being larger than that of the bottom surface of the semiconductor board, which contacts the insulating layer, and a gate electrode formed on the channel region via a gate insulating layer.Type: ApplicationFiled: February 21, 2003Publication date: December 11, 2003Inventors: Naoharu Sugiyama, Tsutomu Tezuka, Tomohisa Mizuno, Shinichi Takagi
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Publication number: 20030193060Abstract: A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.Type: ApplicationFiled: May 19, 2003Publication date: October 16, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomohisa Mizuno, Naoharu Sugiyama, Shinichi Takagi
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Patent number: 6607948Abstract: A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.Type: GrantFiled: August 24, 2001Date of Patent: August 19, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Atsushi Kurobe, Tsutomu Tezuka, Tomohisa Mizuno, Shinichi Takagi
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Patent number: 6583437Abstract: A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.Type: GrantFiled: March 19, 2001Date of Patent: June 24, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Tomohisa Mizuno, Naoharu Sugiyama, Shinichi Takagi
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Patent number: 6509587Abstract: High-speed and low-power-consuming transistors such as field effect transistors having strained Si channels and hetero-bipolar transistors are integrated with each other. Used here is a complex structure in which an MOSFET having a thin-film SiGe buffer layer and a strained Si channel are laminated on an insulating film and an HBT having an SiGe base layer formed on a thin-film SiGe layer by epitaxial growth and an Si emitter layer formed on the SiGe base layer are combined with each other. The thin-film SiGe layer formed on the insulating film of the MOSFET is made thinner than the counterpart of the HBT. The thin-film SiGe layer formed on the insulating film of the MOSFET has Ge concentration higher than that of the counterpart of the HBT.Type: GrantFiled: September 19, 2001Date of Patent: January 21, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Tsutomu Tezuka, Tomohisa Mizuno, Shinichi Takagi
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Publication number: 20020038898Abstract: High-speed and low-power-consuming transistors such as field effect transistors having strained Si channels and hetero-bipolar transistors are integrated with each other. Used here is a complex structure in which an MOSFET having a thin-film SiGe buffer layer and a strained Si channel are laminated on an insulating film and an HBT having an SiGe base layer formed on a thin-film SiGe layer by epitaxial growth and an Si emitter layer formed on the SiGe base layer are combined with each other. The thin-film SiGe layer formed on the insulating film of the MOSFET is made thinner than the counterpart of the HBT. The thin-film SiGe layer formed on the insulating film of the MOSFET has Ge concentration higher than that of the counterpart of the HBT.Type: ApplicationFiled: September 19, 2001Publication date: April 4, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoharu Sugiyama, Tsutomu Tezuka, Tomohisa Mizuno, Shinichi Takagi
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Publication number: 20010048119Abstract: A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.Type: ApplicationFiled: March 19, 2001Publication date: December 6, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomohisa Mizuno, Naoharu Sugiyama, Shinichi Takagi