Patents by Inventor Tomohisa Motoki

Tomohisa Motoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Read-out circuit in semiconductor memory device
    Patent number: 7359247
    Abstract: A read-out circuit comprises a read-out voltage generator circuit converting a memory cell current into a read-out voltage, a reference voltage generator circuit supplying a reference memory cell corresponding to each memory state intermediate between multilevel data with a reference current from a reference loading circuit and converting the reference current flowing through the reference memory cell sequentially selected into a reference voltage. The reference voltage generator circuit modifies the current supply capability of the reference loading circuit corresponding to a change in the selection of the reference memory cell to suppress a change in the reference voltage derived from a change in the reference current and the read-out voltage generator circuit modifies the current supply capability of the main loading circuit corresponding to a change in the selection of the reference memory cell to increase or decrease in proportion to the current supply capability of the reference loading circuit.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: April 15, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomohisa Motoki
  • Read-out circuit in semiconductor memory device
    Publication number: 20070019469
    Abstract: A read-out circuit comprises a read-out voltage generator circuit converting a memory cell current into a read-out voltage, a reference voltage generator circuit supplying a reference memory cell corresponding to each memory state intermediate between multilevel data with a reference current from a reference loading circuit and converting the reference current flowing through the reference memory cell sequentially selected into a reference voltage. The reference voltage generator circuit modifies the current supply capability of the reference loading circuit corresponding to a change in the selection of the reference memory cell to suppress a change in the reference voltage derived from a change in the reference current and the read-out voltage generator circuit modifies the current supply capability of the main loading circuit corresponding to a change in the selection of the reference memory cell to increase or decrease in proportion to the current supply capability of the reference loading circuit.
    Type: Application
    Filed: July 21, 2006
    Publication date: January 25, 2007
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Tomohisa Motoki