Patents by Inventor Tomoki Suemasa

Tomoki Suemasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9418866
    Abstract: A gas processing method is described. A workpiece is mounted on a platform in a chamber on which a silicon oxide film is formed on a surface of the workpiece; HF gas and a NH3 gas, as reaction gases, are discharged onto the workpiece on the platform from a plurality of gas discharge holes of a shower plate; and a treatment for causing a reaction between the reaction gases and the silicon oxide film on the surface of the workpiece is performed. Subsequently, the reaction product resulting from the treatment is heated and removed by decomposition, whereby etching is performed. The shower plate is divided into a plurality of regions in correspondence with the workpiece, and the gas discharge holes in one or more of the regions are blocked to control a distribution of at least one of the HF gas and the NH3 gas.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 16, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Tomoki Suemasa
  • Patent number: 9384993
    Abstract: An oxide etching method includes loading an object to be processed, on a surface of which a patterned silicon oxide film is formed, in a chamber, supplying HF gas and NH3 gas as reactant gases and a diluent gas to the chamber to conduct a reaction treatment in which the HF gas and the NH3 gas are reacted with the silicon oxide film. Thereafter, a heating process is performed to remove a reaction product generated by the reaction treatment. In the reaction treatment, a pressure in the chamber is increased to a predetermined value by increasing a flow rate of the diluent gas so that no etching residue remains and an etching shape has high verticality after the heating process.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: July 5, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Tomoki Suemasa
  • Publication number: 20150170931
    Abstract: A gas processing method is described. A workpiece is mounted on a platform in a chamber on which a silicon oxide film is formed on a surface of the workpiece; HF gas and a NH3 gas, as reaction gases, are discharged onto the workpiece on the platform from a plurality of gas discharge holes of a shower plate; and a treatment for causing a reaction between the reaction gases and the silicon oxide film on the surface of the workpiece is performed. Subsequently, the reaction product resulting from the treatment is heated and removed by decomposition, whereby etching is performed. The shower plate is divided into a plurality of regions in correspondence with the workpiece, and the gas discharge holes in one or more of the regions are blocked to control a distribution of at least one of the HF gas and the NH3 gas.
    Type: Application
    Filed: May 21, 2013
    Publication date: June 18, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Tomoki Suemasa
  • Publication number: 20150079801
    Abstract: An oxide etching method includes loading an object to be processed, on a surface of which a patterned silicon oxide film is formed, in a chamber, supplying HF gas and NH3 gas as reactant gases and a diluent gas to the chamber to conduct a reaction treatment in which the HF gas and the NH3 gas are reacted with the silicon oxide film. Thereafter, a heating process is performed to remove a reaction product generated by the reaction treatment. In the reaction treatment, a pressure in the chamber is increased to a predetermined value by increasing a flow rate of the diluent gas so that no etching residue remains and an etching shape has high verticality after the heating process.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Inventor: Tomoki SUEMASA
  • Patent number: 7326650
    Abstract: In an etching method for achieving a dual damascene structure by using at least one layer of a low-k film and at least one layer of a hard mask, a dummy film, which is ultimately not left in the dual damascene structure, is formed in at least one layer over the hard mask in order to prevent shoulder sag. By adopting this method, a dual damascene structure in which the extent of the shoulder sag at the hard mask is minimized can be achieved through etching.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: February 5, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Yoshihide Kihara, Shin Okamoto, Koichiro Inazawa, Tomoki Suemasa
  • Publication number: 20040173573
    Abstract: The present invention provides an oxide film etching method performed by using an etching apparatus in which an oxide film formed on a target object to be processed is etched by utilizing a plasma generated within the process chamber by application of a high frequency power. The etching gas introduced into the process chamber in the etching step contains a C4F6 gas and an O2 gas, and the ratio C4F6/O2 of the C4F6 gas to the O2 gas falls within a range of 0.7 and 1.5 so as to increase the etching selectivity of the oxide film relative to a resist film.
    Type: Application
    Filed: March 24, 2004
    Publication date: September 9, 2004
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yoshiki Igarashi, Vaidya Nathan Balasubramaniam, Tomoki Suemasa, Koichiro Inazawa
  • Publication number: 20040026364
    Abstract: In an etching method for achieving a dual damascene structure by using at least one layer of a low-k film and at least one layer of a hard mask, a dummy film, which is ultimately not left in the dual damascene structure, is formed in at least one layer over the hard mask in order to prevent shoulder sag. By adopting this method, a dual damascene structure in which the extent of the shoulder sag at the hard mask is minimized can be achieved through etching.
    Type: Application
    Filed: August 18, 2003
    Publication date: February 12, 2004
    Inventors: Yoshihide Kihara, Shin Okamoto, Koichiro Inazawa, Tomoki Suemasa
  • Patent number: 6670276
    Abstract: A wafer W is placed on a lower electrode 106 provided inside a processing chamber 102 of a plasma processing apparatus 100. A film constituted an organic polysiloxane, which is a Low-K material is formed at the wafer W. Plasma is generated inside the processing chamber 102 to implement an etching process by using a photoresist film on the organic polysiloxane film as a mask and an opening pattern in which a portion of the organic polysiloxane film is exposed is formed. After the etching process, the wafer W is left inside the processing chamber 102. The pressure inside the processing chamber 102 is set at a level within the range of 30 mTorr (4.00 Pa)˜150 mTorr (20.0 Pa) by inducing a processing gas into the processing chamber 102 and evacuating the gas from the processing chamber 102. At the pressure level the set, the gas inside the processing chamber 102 is raised to plasma and the photoresist film is ashed.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: December 30, 2003
    Assignee: Tokyo Electron Limited
    Inventors: Tomoki Suemasa, Vaidyanathan Balasubramaniam, Koichiro Inazawa
  • Patent number: 6642149
    Abstract: In a processing chamber of an etching apparatus a lower electrode and an upper electrode grounded through a processing container are disposed oppositely to each other. A first high frequency power supply section composed of a first filter, a first matching device, and a first power source, and a second high frequency power supply section composed of a second filter, a second matching device, and a second power source are connected to the lower electrode. A superimposed power of two frequencies composed of a first high frequency power component of at least 10 MHz produced from the first power source and a second high frequency power component of at least 2 MHz produced from the second power source is applied to the lower electrode. Ions in the plasma do not accelerated by changes of electric field in the processing chamber, but are accelerated by a self-bias voltage and collide only against a wafer on the lower electrode.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: November 4, 2003
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Tomoki Suemasa, Tsuyoshi Ono, Kouichiro Inazawa, Makoto Sekine, Itsuko Sakai, Yukimasa Yoshida
  • Publication number: 20030102087
    Abstract: In a plasma processing apparatus of this invention, a ring-like segment magnet is formed around an upper portion of a chamber so a magnetic field is generated around a processing space. The segment magnet can be rotated by a rotating mechanism in the circumferential direction of the chamber. A magnetic field is generated around the processing space by a magnetic field generating means. That position where a substrate to be processed is present is set in a substantial non-magnetic field state, so charge-up damage is prevented. Due to the plasma confining effect of this magnetic field, the plasma processing rate of the substrate to be processed is set to be almost equal between the edge and center of the substrate to be processed, thereby making the processing rate uniform. A pivoting means is provided so as to alter the gap between the magnets or directions of magnetization thereof.
    Type: Application
    Filed: November 29, 2002
    Publication date: June 5, 2003
    Inventors: Youbun Ito, Takayuki Katsunuma, Koichiro Inazawa, Tomoki Suemasa, Jun Hirose, Hiroo Ono, Kazuya Nagaseki
  • Publication number: 20030054647
    Abstract: In a processing chamber of an etching apparatus a lower electrode and an upper electrode grounded through a processing container are disposed oppositely to each other. A first high frequency power supply section composed of a first filter, a first matching device, and a first power source, and a second high frequency power supply section composed of a second filter, a second matching device, and a second power source are connected to the lower electrode. A superimposed power of two frequencies composed of a first high frequency power component of at least 10 MHz produced from the first power source and a second high frequency power component of at least 2 MHz produced from the second power source is applied to the lower electrode. Ions in the plasma do not accelerated by changes of electric field in the processing chamber, but are accelerated by a self-bias voltage and collide only against a wafer on the lower electrode.
    Type: Application
    Filed: November 4, 2002
    Publication date: March 20, 2003
    Inventors: Tomoki Suemasa, Tsuyoshi Ono, Kouichiro Inazawa, Makoto Sekine, Itsuko Sakai, Yukimasa Yoshida
  • Publication number: 20020055263
    Abstract: The present invention provides an oxide film etching method performed by using an etching apparatus in which an oxide film formed on a target object to be processed is etched by utilizing a plasma generated within the process chamber by application of a high frequency power. The etching gas introduced into the process chamber in the etching step contains a C4F6 gas and an O2 gas, and the ratio C4F6/O2 of the C4F6 gas to the O2 gas falls within a range of 0.7 and 1.5 so as to increase the etching selectivity of the oxide film relative to a resist film.
    Type: Application
    Filed: September 21, 2001
    Publication date: May 9, 2002
    Inventors: Yoshiki Igarashi, Vaidya Nathan Balasubramaniam, Tomoki Suemasa, Koichiro Inazawa
  • Patent number: 6089181
    Abstract: In a plasma etching apparatus, a process gas is supplied into a process chamber and converted into plasma by means of RF discharge, and a semiconductor wafer placed on a lower electrode is etched by the plasma. An RF power supply mechanism is connected to the lower electrode for applying thereto a superposed RF power for forming an RF electric field in the process chamber. The RF power supply mechanism has first and second RF power supplies for respectively oscillating a low frequency RF component and a high frequency RF component having a higher frequency than the low frequency RF component. The high frequency RF component from the second frequency RF component supply has its wave form modulated by a modulator on the basis of the wave form of the low frequency RF component from the first frequency RF power supply. Thereafter, the modulated high frequency RF component and the low frequency RF component are superposed upon each other.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: July 18, 2000
    Assignee: Tokyo Electron Limited
    Inventors: Tomoki Suemasa, Tsuyoshi Ono, Kouichiro Inazawa