Patents by Inventor Tomoko Miyashita

Tomoko Miyashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240077373
    Abstract: A force sensor module according to an embodiment of the present disclosure includes a plurality of force sensors. Each of the force sensor includes a plurality of sensor sections having force detection directions different from each other, and a flexible rubber member that is provided to cover the plurality of sensor sections. The rubber member is configured to transmit a force inputted from outside to the plurality of force sensors by deformation corresponding to the force.
    Type: Application
    Filed: December 16, 2021
    Publication date: March 7, 2024
    Inventors: TOMOKO KATSUHARA, HIDETOSHI MIYASHITA, RUI KAMADA, KIYOKAZU MIYAZAWA, TOSHIMITSU TSUBOI, HAYATO HASEGAWA
  • Publication number: 20230334252
    Abstract: An information processing device includes an analyzing unit configured to analyze text data representing claims included in patent document data to identify constituent components of an invention for each claim included in the claims, and a display control unit configured to cause a display device to display texts indicating each claim in the claims, in a form in which the texts indicating each claim are partitioned into the constituent components.
    Type: Application
    Filed: December 17, 2020
    Publication date: October 19, 2023
    Inventors: Chinatsu TANABE, Hiroko TAKASHI, Nao TAKEUCHI, Eriko TAKEDA, Kenichiro NAKAJIMA, Tomoko MIYASHITA
  • Patent number: 6768205
    Abstract: The objective of the present invention is to provide a reliable thin-film circuit substrate or via formed substrate that is provided with minute via plugs at a fine pitch. The objective is served by forming an insulation layer that functions as an etching stopper on a Si substrate, and then via holes are formed in the Si substrate, using a semiconductor process, until the etching stopper layer is exposed. Further, a thin-film circuit is formed on the insulation layer, and the insulation layer is removed at the via holes such that the thin-film circuit is exposed. As necessary, the thin film circuit is heat-treated, and then the via holes are filled with an electrically conductive material and vamp electrodes are formed.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: July 27, 2004
    Assignee: Fujitsu Limited
    Inventors: Osamu Taniguchi, Tomoko Miyashita, Yasuo Yamagishi, Koji Omote, Yoshihiko Imanaka
  • Publication number: 20030045085
    Abstract: The objective of the present invention is to provide a reliable thin-film circuit substrate or via formed substrate that is provided with minute via plugs at a fine pitch. The objective is served by forming an insulation layer that functions as an etching stopper on a Si substrate, and then via holes are formed in the Si substrate, using a semiconductor process, until the etching stopper layer is exposed. Further, a thin-film circuit is formed on the insulation layer, and the insulation layer is removed at the via holes such that the thin-film circuit is exposed. As necessary, the thin film circuit is heat-treated, and then the via holes are filled with an electrically conductive material and vamp electrodes are formed.
    Type: Application
    Filed: March 1, 2002
    Publication date: March 6, 2003
    Applicant: Fujitsu Limited
    Inventors: Osamu Taniguchi, Tomoko Miyashita, Yasuo Yamagishi, Koji Omote, Yoshihiko Imanaka