Abstract: Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the semiconductor chip. In addition, the separating region is put in contact with the entire side faces of the semiconductor chip.

Abstract: Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the semiconductor chip. In addition, the separating region is put in contact with the entire side faces of the semiconductor chip.

Abstract: Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the semiconductor chip. In addition, the separating region is put in contact with the entire side faces of the semiconductor chip.

Abstract: Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the semiconductor chip. In addition, the separating region is put in contact with the entire side faces of the semiconductor chip.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate of a first conductive type, a first well of a second conductive type provided in the semiconductor substrate, a second well of the first conductive type provided in the first well, a third well of the second conductive type provided in the semiconductor substrate, a fourth well of the first conductive type provided in the third well, semiconductor elements constructing a first functional integrated circuit provided in the first and second wells, semiconductor elements constructing a second functional integrated circuit provided in the third and fourth wells, and an internal power source voltage generating circuit provided in the first well. The internal power source voltage generating circuit configured to generate a first internal power source voltage is applied to the first functional integrated circuit and a second internal power source voltage is applied to the second functional integrated circuit.

Abstract: Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the semiconductor chip. In addition, the separating region is put in contact with the entire side faces of the semiconductor chip.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate of a first conductive type, a first well of a second conductive type provided in the semiconductor substrate, a second well of the first conductive type provided in the first well, a third well of the second conductive type provided in the semiconductor substrate, a fourth well of the first conductive type provided in the third well, semiconductor elements constructing a first functional integrated circuit provided in the first and second wells, semiconductor elements constructing a second functional integrated circuit provided in the third and fourth wells, and an internal Power source voltage generating circuit provided in the first well. The internal power source voltage generating circuit configured to generate a first internal power source voltage is applied to the first functional integrated circuit and a second internal power source voltage is applied to the second functional integrated circuit.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type, at least one first well of a second conductivity type formed in the semiconductor substrate, and at least one second well of the first conductivity type formed in at least one first well. The semiconductor device is composed of semiconductor circuits each formed in at least one first well and at least one second well.

Abstract: A method for testing a semiconductor device comprises executing a function test on the semiconductor device, executing a DC characteristic test on the semiconductor device, executing a remedy determination process of the semiconductor device, and executing a remedy process on the semiconductor device. The remedy determination process is performed in parallel to the DC test.

Abstract: A tester is designed to test a semiconductor memory device. First of all, the tester executes the function test of a memory cell array, which is among the function tests of the semiconductor device. Then, the tester performs redundancy analysis to replace an abnormal portion of the memory cell array with a spare row/column. The tester also executes the DC characteristic test of the semiconductor memory device and the function test of a peripheral circuit of the semiconductor memory device. The redundancy analysis is performed in parallel to both the DC characteristic test and the function test of the peripheral circuit.

Abstract: A tester is designed to test a semiconductor memory device. First of all, the tester executes the function test of a memory cell array, which is among the function tests of the semiconductor device. Then, the tester performs redundancy analysis to replace an abnormal portion of the memory cell array with a spare row/column. The tester also executes the DC characteristic test of the semiconductor memory device and the function test of a peripheral circuit of the semiconductor memory device. The redundancy analysis is performed in parallel to both the DC characteristic test and the function test of the peripheral circuit.

Abstract: A tester is designed to test a semiconductor memory device. First of all, the tester executes the function test of a memory cell array, which is among the function tests of the semiconductor device. Then, the tester performs redundancy analysis to replace an abnormal portion of the memory cell array with a spare row/column. The tester also executes the DC characteristic test of the semiconductor memory device and the function test of a peripheral circuit of the semiconductor memory device. The redundancy analysis is performed in parallel to both the DC characteristic test and the function test of the peripheral circuit.

Abstract: Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the semiconductor chip. In addition, the separating region is put in contact with the entire side faces of the semiconductor chip.

Abstract: A semiconductor device having a multi-bit data input/output terminal is tested or inspected by use of a conventional testing apparatus. The semiconductor device is divided into a number of memory cell blocks, and test data comprised of a limited number of bits corresponding to the number of bits of the data I/O terminal of each memory cell block is supplied to each memory cell block. Each memory cell block has a buffer circuit located between adjacent ones of the data buses corresponding to the respective I/O terminals. Each memory cell block also has first to test buffer circuits. The test buffer circuits include an i-th test buffer circuit (i a natural number in the range of) which has one connected to the first data bus and the other end connected to the data bus. The first to n-th buffer circuits and the first to test buffer circuits are switched between active and inactive by controlling timing signals supplied thereto.

Abstract: A semiconductor integrated circuit device comprises, on a semiconductor chip, a large-scale memory as a main memory, a controller for controlling at least inputting data from the outside of the chip to the large-scale memory, and outputting data from the large-scale memory to the outside of the chip, and a self-test circuit for testing the large-scale memory. The self-test circuit includes a rewritable EEPROM, into which a self-test sequence is written. The self-test circuit tests the large-scale memory in accordance with the self-test sequence written in the EEPROM.

Abstract: A probe card which can help to enhance the productivity of semiconductor integrated circuits manufacturing and to reduce the manufacturing cost thereof, and a method of probe-testing semiconductor integrated circuits by using the probe card. The probe card is designed to test semiconductor integrated circuits formed on a semiconductor wafer and arranged in rows and columns. It has groups of probe needles provided to contact semiconductor integrated circuits arranged in two columns and at least two rows. The card receives a test signal from a test device and supplies the test signal simultaneously to these semiconductor integrated circuits arranged in two columns and at least tow rows, through the groups of probe needles. It receives response signals simultaneously from the semiconductor integrated circuits through the groups of probe needles and then supplies the response signals to the tester.

Abstract: A wafer prober comprises a wafer chuck for chucking a wafer and a probe card holding section for holding two or more probe cards. The wafer prober further comprises a test section for simultaneously testing a plurality of chips among chips in one wafer, with use of the two or more probe cards, while respectively making probe sections included in the two or more probe cards be in contact with external terminal sections of the plurality of chips.

Abstract: A probe card which can help to enhance the productivity of semiconductor integrated circuits manufacturing and to reduce the manufacturing cost thereof, and a method of probe-testing semiconductor integrated circuits by using the probe card. The probe card is designed to test semiconductor integrated circuits formed on a semiconductor wafer and arranged in rows and columns. It has groups of probe needles provided to contact semiconductor integrated circuits arranged in two columns and at least two rows. The card receives a test signal from a test device and supplies the test signal simultaneously to these semiconductor integrated circuits arranged in two columns and at least two row, through the groups of probe needles. It receives response signals simultaneously from the semiconductor integrated circuits through the groups of probe needles and then supplies the response signals to the tester.

Abstract: A probe card which can help to enhance the productivity of semiconductor integrated circuits manufacturing and to reduce the manufacturing cost thereof, and a method of probe-testing semiconductor integrated circuits by using the probe card. The probe card is designed to test semiconductor integrated circuits formed on a semiconductor wafer and arranged in rows and columns. It has groups of probe needles provided to contact semiconductor integrated circuits arranged in two columns and at least two rows. The card receives a test signal from a test device and supplies the test signal simultaneously to these semiconductor integrated circuits arranged in two columns and at least tow rows, through the groups of probe needles. It receives response signals simultaneously from the semiconductor integrated circuits through the groups of probe needles and then supplies the response signals to the tester.