Abstract: In the present invention, a main switch circuit (13) is provided between an electric power line (PL), to which voltage outputted from a solar cell (11) is applied, and a battery module (12). A protection circuit (19) turns OFF the main switch circuit (13) to protect the battery module (12) from overcharging when the voltage (VBAT) of the battery module (12) is equal to or greater than an upper limit voltage. The voltage outputted from the solar cell (11) is set so as to be greater than the upper limit voltage to allow the battery module (12) to be charged to the upper limit voltage. When a charge ON command signal has been received, a control unit (18) turns ON only a sub-switch circuit (14) to introduce current from the solar cell (11) into a parallel circuit (15) and to suppress the voltage (VPL) of the power line (PL) to less than the upper limit voltage before turning ON the main switch circuit (13).

Abstract: A ground fault detection circuit includes: a first switch circuit that connects/disconnects a first path between a positive bus bar and a ground potential section, the positive bus bar being connected to positive electrodes of secondary battery units through a field-effect transistor including a parasitic diode; a second switch circuit that connects/disconnects a second path between a negative bus bar and a ground potential section, the negative bus bar being connected to negative electrodes of the secondary battery units; and a ground fault detection unit that detects a ground fault of the positive bus bar or the negative bus bar based on an electric current flowing through the first path or the second path.

Abstract: A ground fault detection circuit may include a switch circuit that connects or disconnects a path between a bus bar connected to a secondary battery and a ground potential section; an I/V conversion resistance element for detecting a ground fault of the bus bar based on an electric current flowing through the path; and a resistance element connected in series to the I/V conversion resistance element.

Abstract: In the present invention, a main switch circuit (13) is provided between an electric power line (PL), to which voltage outputted from a solar cell (11) is applied, and a battery module (12). A protection circuit (19) turns OFF the main switch circuit (13) to protect the battery module (12) from overcharging when the voltage (VBAT) of the battery module (12) is equal to or greater than an upper limit voltage. The voltage outputted from the solar cell (11) is set so as to be greater than the upper limit voltage to allow the battery module (12) to be charged to the upper limit voltage. When a charge ON command signal has been received, a control unit (18) turns ON only a sub-switch circuit (14) to introduce current from the solar cell (11) into a parallel circuit (15) and to suppress the voltage (VPL) of the power line (PL) to less than the upper limit voltage before turning ON the main switch circuit (13).

Abstract: A ground fault detection circuit includes: a first switch circuit that connects/disconnects a first path between a positive bus bar and a ground potential section, the positive bus bar being connected to positive electrodes of secondary battery units through a field-effect transistor including a parasitic diode; a second switch circuit that connects/disconnects a second path between a negative bus bar and a ground potential section, the negative bus bar being connected to negative electrodes of the secondary battery units; and a ground fault detection unit that detects a ground fault of the positive bus bar or the negative bus bar based on an electric current flowing through the first path or the second path.

Abstract: An image signal is input to two LPFs having different transmission characteristics. A selector chooses one of outputs of the respective LPFs and delivers the chosen output to a gamma correction circuit. The switching of the selector is controlled by a filter control circuit. In the filter control circuit, a comparator compares an exposure time E of a current frame with a threshold value R. The selector is controlled so as to select an output of one of the LPFs that has a lower cutoff frequency and a greater noise component elimination effect than the other LPF does if the exposure time E is longer than or equal to the threshold value R.

Abstract: In exposure control of an imaging apparatus, if a vertical scanning period is enlarged to increase an exposure time when the exposure time reaches an upper limit value, there occurs a problem in that a frame rate is reduced. Accordingly, when a subject is dark, an auto exposure control circuit sets the vertical scanning period V to a standard value Vst, increases the exposure time E to the upper limit value Emax (P60) and then increases a gain ? of an AGC circuit (P62). If the image is still dark even when the gain ? reaches the upper limit value ? max, the auto exposure control circuit switches the vertical scanning period V to an enlarged value Vex and thus more increases the exposure time E (P64).

Abstract: Image data of a target pixel and peripheral pixels are stored in a memory. Using a most significant bit extractor circuit, 4 most significant bits of data are extracted from each image data. A histogram circuit generates a histogram of the extracted 4-bit data. Referring to the histogram, a data processor circuit (17) replaces the image data of the target pixel with a maximum value of the numbers of pixels having the same level and outputs the processed data. Then, a digit-complementing circuit converts the data output from the data processor circuit to 8-bit data and outputs the converted data. In this manner, a regular image is converted into an image similar to a draft-design image.

Abstract: A first solid state imaging device (20a) captures a first picture of a subject to generate a first image signal Ya(t). A second solid state imaging device (20b) captures a second picture of the subject to generate a second image signal Yb(t). In synchronization with operation of the first and second solid state imaging devices (20a, 20b), a selection circuit (26) alternately selects one of the first and second image signals Ya(t) and Yb(t) to output a selected image signal. A digital processing circuit (29) includes a first register (33a) that stores first exposure data EDa generated in accordance with the first image signal Ya(t), and includes a second register (33b) that stores second exposure data EDb generated in accordance with the second image signal Yb(t). This enables smooth switching of operation between the solid state imaging devices.

Abstract: In a solid-state image pickup apparatus, a level adjustment control circuit sequentially executes a first level adjustment performing a level adjustment of a pickup image signal based on an electronic iris control signal for changing an exposure period in a solid-state image pickup device according to a luminance level of the pickup image signal, a second level adjustment performing the level adjustment of the pickup image signal based on a gain control signal for controlling a gain of a gain variable amplifier amplifying the luminance level of the pickup image signal, and a third level adjustment based on the electronic iris control signal to lengthen the exposure period to be longer than that of the first level adjustment in a second luminance level which is lower than a first luminance level of the pickup image signal and does not continue to the first luminance level.

Abstract: In exposure control of an imaging apparatus, if a vertical scanning period is enlarged to increase an exposure time when the exposure time reaches an upper limit value, there occurs a problem in that a frame rate is reduced. Accordingly, when a subject is dark, an auto exposure control circuit sets the vertical scanning period V to a standard value Vst, increases the exposure time E to the upper limit value Emax (P60) and then increases a gain a of an AGC circuit (P62). If the image is still dark even when the gain ? reaches the upper limit value amax, the auto exposure control circuit switches the vertical scanning period V to an enlarged value Vex and thus more increases the exposure time E (P64).

Abstract: An imaging apparatus having a solid-state image sensor, such as a CCD, accumulates information charges corresponding to an image of an object and generates an image signal using the stored charges. A driver provides clock signals to the sensor which define vertical and horizontal scan periods, so that the information charges are accumulated in a predetermined exposure period, in accordance with a timing signal. A first exposure information generating circuit determines whether a level of the image signal is within an appropriate range and produces first exposure information based on the determination results. A second exposure information generating circuit calculates second exposure information using the image signal. A selector selects the first exposure information when the level of the image signal is outside of the predetermined exposure period and selects the second exposure information when the image signal is within the predetermined exposure period.

Abstract: In a processor for performing image signal processing including gamma correction processing for performing nonlinear conversion, S/N deterioration in the increase of a gain such as AGC, etc. is restrained and a dynamic range is secured. Plural converting characteristic functions 90, 92, 94 used in a gamma correcting circuit are stored to the processor in advance. When both an exposure time E and a gain G are small, a characteristic setting circuit sets standard characteristics 90 to the gamma correcting circuit. When the exposure time E is large and the gain G is small, the characteristic setting circuit switches the converting characteristics to correcting characteristics 92 for setting an inclination to be small at a low signal level and restrains the amplification of a noise level at the low signal level.

Abstract: An image signal processing apparatus solves a problem of an increase in noise component contained in an image signal due to the gamma correction when a signal level is in a region where a slope of conversion characteristic is sharp, which problem has been detected in an image signal processing apparatus including gamma correction processing performed for achieving nonlinear conversion. The image signal is input to each of LPFs 40 and 42 which differ in transmission characteristic, and a selector 44 selects either one of outputs from the LPFs to send the selected output to the gamma correction circuit. The switching by the selector 44 is controlled by the filter control circuit 32. In the filter control circuit 32, a comparator 60 compares a signal level of an object pixel with a threshold value R.

Abstract: An image signal is input to two LPFs having different transmission characteristics. A selector chooses one of outputs of the respective LPFs and delivers the chosen output to a gamma correction circuit. The switching of the selector is controlled by a filter control circuit. In the filter control circuit, a comparator compares an exposure time E of a current frame with a threshold value R. The selector is controlled so as to select an output of one of the LPFs that has a lower cutoff frequency and a greater noise component elimination effect than the other LPF does if the exposure time E is longer than or equal to the threshold value R.

Abstract: A frame transfer type solid-state imaging apparatus has a matrix of pixels which store information charges corresponding to a received image. The information charges are moved from the pixels to vertical transfer registers, and then to a horizontal transfer register, prior to being stored. A timing control circuit generates a vertical scan timing signal and a horizontal scan timing signal using a divided clock signal. A horizontal drive circuit generates a horizontal transfer clock using the divided clock signal and the horizontal scan timing signal. The horizontal transfer clock is used to move the information charges from the vertical transfer registers to the horizontal transfer register. A vertical drive circuit generates a vertical transfer clock using a reference clock signal and the vertical scan timing signal. The vertical transfer clock is used to move the information charges from the pixels to the vertical transfer registers.

Abstract: Exposure control for a solid-state imaging apparatus can be completed in a short time. First exposure information D1 and second exposure information D2 are prepared. The first exposure information D1 is for adjustment of an exposure time L for a CCD (1) through extension or reduction in the unit of one horizontal scanning period; the second exposure information D2 is for direct designation of an exposure time L. When the power is switched on, the second exposure information D2 is selected for supply to a timing control circuit (3). After a lapse of a predetermined time, the first exposure information D1 is then selected.

Abstract: A solid-state imaging apparatus having a CCD image capturing circuit includes an exposure time control circuit which analyzes the image signal generated by the image capturing circuit and generates a control signal to adjust an image exposure time. A balance control circuit also receives the control signal and updates gain control information used by an image processing circuit that generates color difference data (U/V data) from the image signal.

Abstract: Image data of a target pixel and peripheral pixels are stored in a memory. Using a most significant bit extractor circuit, 4 most significant bits of data are extracted from each image data. A histogram circuit generates a histogram of the extracted 4-bit data. Referring to the histogram, a data processor circuit (17) replaces the image data of the target pixel with a maximum value of the numbers of pixels having the same level and outputs the processed data. Then, a digit-complementing circuit converts the data output from the data processor circuit to 8-bit data and outputs the converted data. In this manner, a regular image is converted into an image similar to a draft-design image.

Abstract: A signal level adjusting circuit for performing adjustment of signal levels in which the levels of individual image signals are made uniform so as to provide greater use of a dynamic range on an image sensor without deterioration to resolution.