Patents by Inventor Tomonari Shioda
Tomonari Shioda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955545Abstract: In one embodiment, a semiconductor device includes a substrate, and a first semiconductor layer provided on the substrate and including a first crystal grain. The device further includes a first film provided on a surface of the first semiconductor layer. The device further includes a second semiconductor layer provided on a surface of the first film, provided on the surface of the first semiconductor layer via an opening in the first film, including a second crystal grain, and included in a memory cell. Furthermore, a grain size of the second crystal grain is larger than a maximum value of a width of the second semiconductor layer in the opening.Type: GrantFiled: February 4, 2022Date of Patent: April 9, 2024Assignee: Kioxia CorporationInventor: Tomonari Shioda
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Publication number: 20240098998Abstract: A semiconductor memory device includes: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are stacked one by one alternately; and a pillar that extends in the stacked body in a stacking direction of the stacked body and includes a memory cell formed at each of intersections with the plurality of conductive layers, in which the pillar includes a semiconductor layer extending in the stacking direction, a silicon oxynitride layer covering a side wall of the semiconductor layer, a silicon nitride layer covering a side wall of the silicon oxynitride layer, and a silicon oxide layer covering a side wall of the silicon nitride layer, in which the silicon oxynitride layer has a hydrogen concentration of 1×1020 atm/cc or less in terms of average value.Type: ApplicationFiled: August 29, 2023Publication date: March 21, 2024Inventors: Saori MATSUSHITA, Tomonari SHIODA, Takanori YAMANAKA, Ryota FUJITSUKA
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Publication number: 20230087572Abstract: In one embodiment, a semiconductor device includes a substrate, and a first semiconductor layer provided on the substrate and including a first crystal grain. The device further includes a first film provided on a surface of the first semiconductor layer. The device further includes a second semiconductor layer provided on a surface of the first film, provided on the surface of the first semiconductor layer via an opening in the first film, including a second crystal grain, and included in a memory cell. Furthermore, a grain size of the second crystal grain is larger than a maximum value of a width of the second semiconductor layer in the opening.Type: ApplicationFiled: February 4, 2022Publication date: March 23, 2023Applicant: Kioxia CorporationInventor: Tomonari SHIODA
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Publication number: 20220077286Abstract: A semiconductor device in an embodiment includes a substrate and a transistor. The transistor includes a source layer, a drain layer, a gate insulation film, a gate electrode, a contact plug and a first epitaxial layer. The source layer and the drain layer are provided in surface regions of the substrate, and contain an impurity. The gate insulation film is provided on the substrate between the source layer and the drain layer. The gate electrode is provided on the gate insulation film. The contact plug is provided so as to protrude to the source layer or the drain layer downward of a surface of the substrate. The first epitaxial layer is provided between the contact plug and the source layer or drain layer, and contains both the impurity and carbon.Type: ApplicationFiled: June 17, 2021Publication date: March 10, 2022Applicant: Kioxia CorporationInventors: Tomonari SHIODA, Yasunori OSHIMA, Taichi IWASAKI, Shota YAMAGIWA, Hiroto SAITO
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Publication number: 20210288056Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate, first transistors including a first diffusion layer provided on a surface of the semiconductor substrate and including impurities and carbon, and first contact plugs provided on the first diffusion layer. The first diffusion layer includes a first region being in contact with the first contact plugs and a second region covering the first region. A concentration of the carbon is higher than that of the impurities in the first region as a depth from the surface is larger.Type: ApplicationFiled: September 1, 2020Publication date: September 16, 2021Applicant: Kioxia CorporationInventors: Takayuki ITO, Tomonari SHIODA
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Patent number: 11075122Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate including a first surface, a first contact part provided at a deeper level than the first surface, and a second contact part protruding up to a higher level than the first surface from the first contact part; a stacked body in which insulating layers and electrode layers are alternately stacked on the first surface; and a semiconductor film extending, on the second contact part, in the stacked body in a first direction perpendicular to the first surface. At an interface between the first contact part and the second contact part, a length of the first contact part in a second direction parallel to the first surface is larger than a length of the second contact part in the second direction.Type: GrantFiled: March 6, 2020Date of Patent: July 27, 2021Assignee: Kioxia CorporationInventors: Tomonari Shioda, Takashi Ishida
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Publication number: 20210074592Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate including a first surface, a first contact part provided at a deeper level than the first surface, and a second contact part protruding up to a higher level than the first surface from the first contact part; a stacked body in which insulating layers and electrode layers are alternately stacked on the first surface; and a semiconductor film extending, on the second contact part, in the stacked body in a first direction perpendicular to the first surface. At an interface between the first contact part and the second contact part, a length of the first contact part in a second direction parallel to the first surface is larger than a length of the second contact part in the second direction.Type: ApplicationFiled: March 6, 2020Publication date: March 11, 2021Applicant: Kioxia CorporationInventors: Tomonari SHIODA, Takashi ISHIDA
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Patent number: 10868030Abstract: According to one embodiment, the substrate includes a plurality of protrusions having columnar configurations, and a void being formed below the protrusions. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body contacts the protrusion and extends through the stacked body in a stacking direction of the stacked body. Upper ends of the protrusions are positioned at a height between a lowermost electrode layer and an electrode layer of a second layer from a bottom of the electrode layers.Type: GrantFiled: March 8, 2018Date of Patent: December 15, 2020Assignee: Toshiba Memory CorporationInventors: Tomonari Shioda, Tatsuo Ishida
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Patent number: 10665608Abstract: A semiconductor device according to an embodiment includes a substrate. A transistor includes a source layer and a drain layer that are provided in a surface region of the substrate and contain impurities. A gate dielectric film is provided on the substrate between the source layer and the drain layer. A gate electrode is provided on the gate dielectric film. A first epitaxial layer is provided on the source layer or the drain layer. A second epitaxial layer is provided on the first epitaxial layer and contains both the impurities and carbon. A contact plug is provided on the second epitaxial layer. A memory cell array is provided above the transistor.Type: GrantFiled: February 25, 2019Date of Patent: May 26, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomonari Shioda, Junya Fujita, Takayuki Ito
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Publication number: 20190348434Abstract: A semiconductor device according to an embodiment includes a substrate. A transistor includes a source layer and a drain layer that are provided in a surface region of the substrate and contain impurities. A gate dielectric film is provided on the substrate between the source layer and the drain layer. A gate electrode is provided on the gate dielectric film. A first epitaxial layer is provided on the source layer or the drain layer. A second epitaxial layer is provided on the first epitaxial layer and contains both the impurities and carbon. A contact plug is provided on the second epitaxial layer. A memory cell array is provided above the transistor.Type: ApplicationFiled: February 25, 2019Publication date: November 14, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tomonari SHIODA, Junya Fujita, Takayuki Ito
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Patent number: 10438966Abstract: According to one embodiment, the silicon layer includes phosphorus. The buried layer is provided on the silicon layer. The stacked body is provided on the buried layer. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends in a stacking direction of the stacked body through the stacked body and through the buried layer, and includes a sidewall portion positioned at a side of the buried layer. The silicon film is provided between the buried layer and the sidewall portion of the semiconductor body. The silicon film includes silicon as a major component and further includes at least one of germanium or carbon.Type: GrantFiled: March 7, 2018Date of Patent: October 8, 2019Assignee: Toshiba Memory CorporationInventors: Tomonari Shioda, Junya Fujita, Tatsuro Nishimoto, Yoshiaki Fukuzumi, Atsushi Fukumoto, Hajime Nagano
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Publication number: 20190067318Abstract: According to one embodiment, the substrate includes a plurality of protrusions having columnar configurations, and a void being formed below the protrusions. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body contacts the protrusion and extends through the stacked body in a stacking direction of the stacked body. Upper ends of the protrusions are positioned at a height between a lowermost electrode layer and an electrode layer of a second layer from a bottom of the electrode layers.Type: ApplicationFiled: March 8, 2018Publication date: February 28, 2019Applicant: Toshiba Memory CorporationInventors: Tomonari SHIODA, Tatsuo Ishida
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Publication number: 20190067317Abstract: According to one embodiment, the silicon layer includes phosphorus. The buried layer is provided on the silicon layer. The stacked body is provided on the buried layer. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends in a stacking direction of the stacked body through the stacked body and through the buried layer, and includes a sidewall portion positioned at a side of the buried layer. The silicon film is provided between the buried layer and the sidewall portion of the semiconductor body. The silicon film includes silicon as a major component and further includes at least one of germanium or carbon.Type: ApplicationFiled: March 7, 2018Publication date: February 28, 2019Applicant: Toshiba Memory CorporationInventors: Tomonari SHIODA, Junya FUJITA, Tatsuro NISHIMOTO, Yoshiaki FUKUZUMI, Atsushi FUKUMOTO, Hajime NAGANO
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Patent number: 9478706Abstract: According to one embodiment, a semiconductor light emitting device includes: first and second semiconductor layers, a light emitting part, and an In-containing layer. The first semiconductor layer is formed on a silicon substrate via a foundation layer. The light emitting part is provided on the first semiconductor layer, and includes barrier layers and a well layer provided between the barrier layers including Ga1-z1Inz1N (0<z1?1). The second semiconductor layer is provided on the light emitting part. The In-containing layer is provided at at least one of first and second positions. The first position is between the first semiconductor layer and the light emitting part. The second position is between the second semiconductor layer and the light emitting part. The In-containing layer includes In with a composition ratio different from the In composition ratio z1 and has a thickness 10 nm to 1000 nm.Type: GrantFiled: July 8, 2014Date of Patent: October 25, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Jongil Hwang, Tomonari Shioda, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9312436Abstract: According to one embodiment, a nitride semiconductor device includes a first layer and a functional layer. The first layer is formed on an amorphous layer, includes aluminum nitride, and has a compressive strain or a tensile strain. The functional layer is formed on the first layer and includes a nitride semiconductor.Type: GrantFiled: March 15, 2013Date of Patent: April 12, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Ono, Tomonari Shioda, Naoharu Sugiyama, Toshiyuki Oka, Shinya Nunoue
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Publication number: 20150263232Abstract: An optical semiconductor element includes a first nitride semiconductor layer of a first conductivity type, a second nitride semiconductor layer of a second conductivity type, and an active layer provided between the first nitride semiconductor layer and the second nitride semiconductor layer. In the optical semiconductor element, a feature is provided in the active layer, and the second nitride semiconductor layer is provided within the feature of the active layer.Type: ApplicationFiled: September 2, 2014Publication date: September 17, 2015Inventors: Tomonari SHIODA, Koichi TACHIBANA
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Patent number: 9130098Abstract: According to one embodiment, a semiconductor light emitting device includes a light emitting layer, a light transmitting layer and a first semiconductor layer. The light transmitting layer is transmittable with respect to light emitted from the light emitting layer. The first semiconductor layer contacts the light transmitting layer between the light emitting layer and the light transmitting layer. The light transmitting layer has a thermal expansion coefficient larger than a thermal expansion coefficient of the light transmitting layer, has a lattice constant smaller than a lattice constant of the active layer, and has a tensile stress in an in-plane direction.Type: GrantFiled: August 18, 2011Date of Patent: September 8, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Tomonari Shioda, Hisashi Yoshida, Shinya Nunoue
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Patent number: 9065003Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer and configured to emit a light having a peak wavelength of 440 nanometers or more. Tensile strain is applied to the first semiconductor layer. An edge dislocation density of the first semiconductor layer is 5×109/cm2 or less. A lattice mismatch factor between the first semiconductor layer and the light emitting layer is 0.11 percent or less.Type: GrantFiled: February 27, 2012Date of Patent: June 23, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hisashi Yoshida, Koichi Tachibana, Tomonari Shioda, Toshiki Hikosaka, Jongil Hwang, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20150102381Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a low refractive index layer. The first semiconductor layer has a first major surface and a second major surface being opposite to the first major surface. The light emitting layer has an active layer provided on the second major surface. The second semiconductor layer is provided on the light emitting layer. The low refractive index layer covers partially the first major surface and has a refractive index lower than the refractive index of the first semiconductor layer.Type: ApplicationFiled: December 19, 2014Publication date: April 16, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoharu SUGIYAMA, Taisuke Sato, Hiroshi Ono, Satoshi Mitsugi, Tomonari Shioda, Jongil Hwang, Hung Hung, Shinya Nunoue
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Patent number: 8987026Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a light emitting layer, a p-type layer, and a transparent electrode. The n-type layer includes a nitride semiconductor and has a thickness not more than 500 nm. The light emitting layer is provided on the n-type layer. The p-type layer is provided on the light emitting layer and includes a nitride semiconductor. The transparent electrode contacts the n-type layer. The n-type layer is disposed between the transparent electrode and the light emitting layer.Type: GrantFiled: September 25, 2014Date of Patent: March 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Tomonari Shioda, Shigeya Kimura, Koichi Tachibana, Shinya Nunoue