Abstract: According to an embodiment, a magnetic disk device includes a first component and a second component. The first component operates at a voltage of a first value. The second component is connected to the first component by a power line for transmitting power to the first component, and operates at a voltage of a second value. In response to supply of the voltage of the second value, the second component outputs a voltage of a third value smaller than the first value to the power line and measures a fourth value, which is a value of current flowing through the power line. The second component starts output of the voltage of the first value to the power line when the fourth value is smaller than the first threshold, and stops output of the voltage to the power line when the fourth value is larger than the first threshold.

Abstract: According to one embodiment, a disk device includes a disk, a plurality of flash ROMs, a head, a cache memory, and a controller. The controller is configured to execute an operation when supply of power from an external power supply is interrupted while writing of data into the disk is performed by using power supplied from the external power supply, wherein the operation includes writing data stored in the cache memory into the flash ROMs in order, by means of serial communication, by using power supplied from an auxiliary power supply. Here, the controller writes data into a first flash ROM of the plurality of flash ROMs, and, in parallel therewith, reads data from a second flash ROM of the plurality of flash ROMs where writing of data is not performed, by means of serial communication.

Abstract: Disclosed is a PLL circuit of a small circuit size capable of generating clock including a jitter component with ease. A phase comparator 11 compares the phase of an input reference clock signal CKR to the phase of a signal fed back from a frequency divider 14 to route an output signal corresponding to the phase difference to a filter unit 12. The filter unit 12 detects a low frequency component of the output signal of the phase comparator 11 to route the so detected component to a voltage controlled oscillator 13. The voltage controlled oscillator 13 generates, as an output signal CKF, an oscillation signal of an oscillation frequency which is controlled on the basis of the output voltage of the filter unit 12. The frequency divider 14 divides the frequency of the output signal CKF to output the resulting signal to the phase comparator 11.

Abstract: Disclosed is a PLL circuit of a small circuit size capable of generating clock including a jitter component with ease. A phase comparator 11 compares the phase of an input reference clock signal CKR to the phase of a signal fed back from a frequency divider 14 to route an output signal corresponding to the phase difference to a filter unit 12. The filter unit 12 detects a low frequency component of the output signal of the phase comparator 11 to route the so detected component to a voltage controlled oscillator 13. The voltage controlled oscillator 13 generates, as an output signal CKF, an oscillation signal of an oscillation frequency which is controlled on the basis of the output voltage of the filter unit 12. The frequency divider 14 divides the frequency of the output signal CKF to output the resulting signal to the phase comparator 11.