Abstract: An optical disc player enters a sleep (low power consumption) mode when inactive for a predetermined time. The optical disc player includes a buffer RAM for storing index information read from a disc. A refresh circuit is connected to the buffer RAM to refresh the RAM. The refresh circuit includes a reference clock generator which generates a reference clock signal having a predetermined frequency from a reference clock using an oscillator. When the disc player enters the sleep mode, it issues a stop signal to the reference clock generator, which then stops generating the reference clock signal and produces a sleep mode clock signal having a frequency necessary to refresh the buffer RAM. A refresh signal generator circuit connected to the reference clock generator produces a refresh signal for the buffer RAM using the sleep mode clock signal.

Abstract: A control circuit provided in an optical disk apparatus which apparatus has a motor to move an optical pickup unit for performing record/playback control of an optical disk in a radial direction of the optical disk, sets a plurality of concentric annular zones on the optical disk, and performs record/playback control, for each zone, of the optical disk. The control circuit comprises a pulse period detector for detecting pulse periods of a periodic pulse control signal which drives the motor; and a zone determination section that determines the zone which the optical pickup unit is facing on the basis of the number of pulse period detection times detected by the pulse period detector.

Abstract: A slice level control circuit for obtaining optimal filter characteristics depending on optical disc data reading speed or optical disc condition, while achieving superior stability and response with respect to slice level. The control circuit cuts DC components in analog input signals to generate C-cut RF signals having adjusted DC levels. A comparator compares two C-cut RF signals to generate a binary RF signal for driving a charge pump circuit. An analog lowpass filter eliminates high-frequency components from the output signal of the charge pump circuit. An A/D converter circuit converts the cutoff output signal of the analog lowpass filter into a digital value signal according to sampling periods. A digital filter filters the digital value signal. A D/A converter converts the filtered digital value signal into an analog voltage signal. The analog voltage signal controls the slice level of the binary circuit.

Abstract: A counter 11 continuously reads in the EFM signal from a binarizing circuit 4, resets its count value each time the polarity of the EFM signal changes, counts counter clocks higher in frequency than the EFM signal during each EFM period of the EFM signal, and transfers the count values to a FIFO 12 sequentially. The FIFO 12 temporarily stores the count values transferred, and writes a predetermined number of count values into a buffer RAM 7 in a batch each time the predetermined number of count values are stored.

Abstract: An optical disc player enters a sleep (low power consumption) mode when inactive for a predetermined time. The optical disc player includes a buffer RAM for storing index information read from a disc. A refresh circuit is connected to the buffer RAM to refresh the RAM. The refresh circuit includes a reference clock generator which generates a reference clock signal having a predetermined frequency from a reference clock using an oscillator. When the disc player enters the sleep mode, it issues a stop signal to the reference clock generator, which then stops generating the reference clock signal and produces a sleep mode clock signal having a frequency necessary to refresh the buffer RAM. A refresh signal generator circuit connected to the reference clock generator produces a refresh signal for the buffer RAM using the sleep mode clock signal.

Abstract: An optical disc player enters a sleep (low power consumption) mode when inactive for a predetermined time. The optical disc player includes a buffer RAM for storing index information read from a disc. A refresh circuit is connected to the buffer RAM to refresh the RAM. The refresh circuit includes a reference clock generator which generates a reference clock signal having a predetermined frequency from a reference clock using an oscillator. When the disc player enters the sleep mode, it issues a stop signal to the reference clock generator, which then stops generating the reference clock signal and produces a sleep mode clock signal having a frequency necessary to refresh the buffer RAM. A refresh signal generator circuit connected to the reference clock generator produces a refresh signal for the buffer RAM using the sleep mode clock signal.

Abstract: A data recording device for recording data on an optical disc by irradiating a laser pulse on the optical disc while controlling rotation of the optical disc at a constant angular velocity. The device includes a laser condition varying unit that changes a peak value of the laser pulse in accordance with a value relating to a linear velocity of the optical disc at a position at which the laser pulse is irradiated.

Abstract: A memory control circuit for writing or reading digital data at a high speed without increasing access speed to the memory circuit. The memory control circuit includes a control signal generation circuit for generating a first write enable signal and a first read enable signal of a first memory circuit, an address generation circuit for generating an address signal designating a data write address of the first memory circuit and a second memory circuit, and a write data supply circuit for supplying write data to the first and second memory circuits. A shift circuit is connected between the control signal generation circuit and the second memory circuit to generate a second write enable signal and a second read enable signal by shifting the first write enable signal and the first read enable signal by one cycle of a data write cycle or read cycle. The write data is written alternately to the first and second memory circuits in response to the first and second write enable signals.