Patents by Inventor Tomonori Miwa
Tomonori Miwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11264248Abstract: A method of etching a substrate including an etching film and a mask formed on the etching film is provided. The mask includes a first pattern of a first recess having a first opening and a second pattern of a second recess having a second opening. The method includes etching the etching film to a predetermined depth; depositing a protective film on the mask after the etching; and etching the etching film after the depositing. The first opening is smaller than the second opening. As a result of the depositing, the first opening of the first pattern is clogged and the second opening of the second pattern is not clogged.Type: GrantFiled: December 5, 2019Date of Patent: March 1, 2022Assignee: Tokyo Electron LimitedInventors: Yoshimitsu Kon, Atsushi Uto, Lifu Li, Tomonori Miwa
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Publication number: 20200185229Abstract: A method of etching a substrate including an etching film and a mask formed on the etching film is provided. The mask includes a first pattern of a first recess having a first opening and a second pattern of a second recess having a second opening. The method includes etching the etching film to a predetermined depth; depositing a protective film on the mask after the etching; and etching the etching film after the depositing. The first opening is smaller than the second opening. As a result of the depositing, the first opening of the first pattern is clogged and the second opening of the second pattern is not clogged.Type: ApplicationFiled: December 5, 2019Publication date: June 11, 2020Inventors: Yoshimitsu KON, Atsushi UTO, Lifu LI, Tomonori MIWA
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Patent number: 9735025Abstract: A method of etching a first region including a multilayered film, in which first dielectric films and second dielectric films serving as silicon nitride films are alternately stacked, and a second region including a single-layered silicon oxide film is provided. The etching method includes a first plasma process of generating plasma of a first processing gas containing a fluorocarbon gas and an oxygen gas within a processing vessel of a plasma processing apparatus; and a second plasma process of generating plasma of a second processing gas containing a hydrogen gas, nitrogen trifluoride gas and a carbon-containing gas within the processing vessel. A temperature of an electrostatic chuck is set to a first temperature in the first plasma process, and the temperature of the electrostatic chuck is set to a second temperature lower than the first temperature in the second plasma process.Type: GrantFiled: May 27, 2016Date of Patent: August 15, 2017Assignee: TOKYO ELECTRON LIMITEDInventors: Masayuki Sawataishi, Tomonori Miwa, Yuki Kaneko
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Patent number: 9735021Abstract: An etching method of etching a first region including a multilayered film, in which silicon oxide films and silicon nitride films are alternately stacked, and a second region including a single-layered silicon oxide film is provided. The etching method includes a first plasma process of generating plasma of a first processing gas containing a fluorocarbon gas and an oxygen gas within a processing vessel of a plasma processing apparatus; and a second plasma process of generating plasma of a second processing gas containing a hydrogen gas, nitrogen trifluoride gas, a hydrogen bromide gas and a carbon-containing gas within the processing vessel. A temperature of an electrostatic chuck is set to a first temperature in the first plasma process, and the temperature of the electrostatic chuck is set to a second temperature lower than the first temperature in the second plasma process.Type: GrantFiled: May 27, 2016Date of Patent: August 15, 2017Assignee: TOKYO ELECTRON LIMITEDInventors: Masayuki Sawataishi, Tomonori Miwa
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Publication number: 20160351406Abstract: A method of etching a first region including a multilayered film, in which first dielectric films and second dielectric films serving as silicon nitride films are alternately stacked, and a second region including a single-layered silicon oxide film is provided. The etching method includes a first plasma process of generating plasma of a first processing gas containing a fluorocarbon gas and an oxygen gas within a processing vessel of a plasma processing apparatus; and a second plasma process of generating plasma of a second processing gas containing a hydrogen gas, nitrogen trifluoride gas and a carbon-containing gas within the processing vessel. A temperature of an electrostatic chuck is set to a first temperature in the first plasma process, and the temperature of the electrostatic chuck is set to a second temperature lower than the first temperature in the second plasma process.Type: ApplicationFiled: May 27, 2016Publication date: December 1, 2016Inventors: Masayuki Sawataishi, Tomonori Miwa, Yuki Kaneko
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Publication number: 20160351407Abstract: An etching method of etching a first region including a multilayered film, in which silicon oxide films and silicon nitride films are alternately stacked, and a second region including a single-layered silicon oxide film is provided. The etching method includes a first plasma process of generating plasma of a first processing gas containing a fluorocarbon gas and an oxygen gas within a processing vessel of a plasma processing apparatus; and a second plasma process of generating plasma of a second processing gas containing a hydrogen gas, nitrogen trifluoride gas, a hydrogen bromide gas and a carbon-containing gas within the processing vessel. A temperature of an electrostatic chuck is set to a first temperature in the first plasma process, and the temperature of the electrostatic chuck is set to a second temperature lower than the first temperature in the second plasma process.Type: ApplicationFiled: May 27, 2016Publication date: December 1, 2016Inventors: Masayuki Sawataishi, Tomonori Miwa
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Patent number: 9418863Abstract: Disclosed is an etching method for etching an etching target layer. The etching method includes: a first step of depositing a plasma reaction product on a mask layer made of an organic film formed on the etching target layer; and after the first step, a second step of etching the etching target layer. The mask layer includes a coarse region in which a plurality of openings are formed, and a dense region surrounding the coarse region. The mask layer exists more densely in the dense region than in the coarse region. The coarse region includes a first region and a second region positioned close to the dense region compared to the first region. In the second step of the etching method, a width of the openings in the first region becomes narrower than a width of the openings in the second region.Type: GrantFiled: May 12, 2015Date of Patent: August 16, 2016Assignee: TOKYO ELECTRON LIMITEDInventors: Shin Hirotsu, Yoshiki Igarashi, Tomonori Miwa, Hiroshi Okada
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Publication number: 20150332932Abstract: Disclosed is an etching method for etching an etching target layer. The etching method includes: a first step of depositing a plasma reaction product on a mask layer made of an organic film formed on the etching target layer; and after the first step, a second step of etching the etching target layer. The mask layer includes a coarse region in which a plurality of openings are formed, and a dense region surrounding the coarse region. The mask layer exists more densely in the dense region than in the coarse region. The coarse region includes a first region and a second region positioned close to the dense region compared to the first region. In the second step of the etching method, a width of the openings in the first region becomes narrower than a width of the openings in the second region.Type: ApplicationFiled: May 12, 2015Publication date: November 19, 2015Applicant: TOKYO ELECTRON LIMITEDInventors: Shin HIROTSU, Yoshiki IGARASHI, Tomonori MIWA, Hiroshi OKADA
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Patent number: 7658816Abstract: A focus ring and a plasma processing apparatus capable of improving an in-surface uniformity of a surface and reducing occurrences of deposition on a backside surface of a peripheral portion of a semiconductor wafer compared to a conventional case are provided. Installed in a vacuum chamber is a susceptor for mounting the semiconductor wafer thereon and a focus ring is installed to surround the semiconductor wafer mounted on the susceptor. The focus ring includes an annular lower member made of a dielectric, and an annular upper member made of a conductive material and mounted on the lower member. The upper member includes a flat portion which is an outer peripheral portion having a top surface positioned higher than a surface to be processed of the semiconductor wafer W, and an inclined portion which is an inner peripheral portion inclined inwardly.Type: GrantFiled: September 3, 2004Date of Patent: February 9, 2010Assignee: Tokyo Electron LimitedInventors: Akira Koshiishi, Hideaki Tanaka, Nobuyuki Okayama, Masaaki Miyagawa, Shunsuke Mizukami, Wataru Shimizu, Jun Hirose, Toshikatsu Wakaki, Tomonori Miwa, Jun Ooyabu, Daisuke Hayashi
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Publication number: 20070169891Abstract: A focus ring and a plasma processing apparatus capable of improving an in-surface uniformity of a surface and reducing occurrences of deposition on a backside surface of a peripheral portion of a semiconductor wafer compared to a conventional case are provided. Installed in a vacuum chamber is a susceptor for mounting the semiconductor wafer thereon and a focus ring is installed to surround the semiconductor wafer mounted on the susceptor. The focus ring includes an annular lower member made of a dielectric, and an annular upper member made of a conductive material and mounted on the lower member. The upper member includes a flat portion which is an outer peripheral portion having a top surface positioned higher than a surface to be processed of the semiconductor wafer W, and an inclined portion which is an inner peripheral portion inclined inwardly.Type: ApplicationFiled: September 3, 2004Publication date: July 26, 2007Applicant: TOKYO ELECTRON LIMITEDInventors: Akira Koshiishi, Hideaki Tanaka, Nobuyuki Okayama, Masaaki Miyagawa, Shunsuke Mizukami, Wataru Shimizu, Jun Hirose, Toshikatsu Wakaki, Tomonori Miwa, Jun Ooyabu, Daisuke Hayashi