Abstract: A high-frequency switch circuit according to the present invention includes at least a first switch connected between a common terminal and a first terminal, and a second switch connected between the common terminal and a second terminal. Each of the first and second switches includes a plurality of field-effect transistors connected in series and each having a body, a source, a drain, and a gate. A compensation capacitance that compensates a parasitic capacitance generated when the first switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the first switch. A compensation capacitance that compensates a parasitic capacitance generated when the second switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the second switch.

Abstract: A high-frequency switch circuit according to the present invention includes at least a first switch connected between a common terminal and a first terminal, and a second switch connected between the common terminal and a second terminal. Each of the first and second switches includes a plurality of field-effect transistors connected in series and each having a body, a source, a drain, and a gate. A compensation capacitance that compensates a parasitic capacitance generated when the first switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the first switch. A compensation capacitance that compensates a parasitic capacitance generated when the second switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the second switch.

Abstract: A switch circuit includes an input section; an output section; a first series section having an output and comprising at least a first 4-terminal FET connected between the input section and the output section through the output of the first series section; a first shunt section comprising at least a second 4-terminal FET connected between an output of the first series section and a ground; a first control terminal section connected with a gate of the first 4-terminal FET; a second control terminal section connected with a gate of the second 4-terminal FET; and a back gate control terminal section connected with a back gate of each of the first and second 4-terminal FETs. A bias power supply section is configured to apply a reverse bias voltage between the back gate control terminal section and the ground.

Abstract: An object is to provide a conduction switching circuit, an operation method of a conduction switching circuit, and a conduction switching circuit block, which can prevent a leakage of a high frequency signal without insertion loss of a reactance. A conduction switching circuit includes a first MOSFET, a second MOSFET connected to the first MOSFET via a first node, and a first control terminal connected to the first node. The first MOSFET and the second MOSFET are provided so as to be electrically connected in series at ON state. The first control terminal is configured to apply a voltage to the first node so that capacitance of the first MOSFET and the second MOSFET is decreased when the first MOSFET and the second MOSFET are OFF state.

Abstract: A switch circuit comprising a plural of switch elements and a control circuit operative to simultaneously shut off all of the switch elements. When forming a switch device by the combination of plural switch circuits, no other additional switches connected in series in the subsequent stage is required for shutting off unintentional signals from other input terminals.

Abstract: In a semiconductor switch apparatus including an input terminal, an output terminal, an AC ground terminal, a DC ground terminal, at least one series MOS transistor connected between the input terminal and the output terminal, and at least one shunt MOS transistor connected between one of the input terminal and the output terminal and the AC ground terminal, the series MOS transistor is formed within a first region of a semiconductor layer on a silicon-on-insulator configuration surrounded by a first trench insulating layer, and the shunt MOS transistor is formed within a second region of the semiconductor layer surrounded by a second trench insulating layer.

Abstract: In a semiconductor switch apparatus including an input terminal, an output terminal, an AC ground terminal, a DC ground terminal, at least one series MOS transistor connected between the input terminal and the output terminal, and at least one shunt MOS transistor connected between one of the input terminal and the output terminal and the AC ground terminal, the series MOS transistor is formed within a first region of a semiconductor layer on a silicon-on-insulator configuration surrounded by a first trench insulating layer, and the shunt MOS transistor is formed within a second region of the semiconductor layer surrounded by a second trench insulating layer.