Abstract: A vector processor in which input/output of vector data to and from a vector register is effected by a load/store pipeline from a main memory, includes a load pipe for reading data of a plural-byte width from the main memory in one access, a plurality of vector registers for storing data read by the load pipe, each having a plurality of entries of an 8-byte width, mark bit stacks provided one for each of the vector registers and each having at least the same number of entries as those of the vector register, the entries of each mark bit stack storing mark bits for indicating which one of the plural-byte data stored in the entries of the corresponding vector register is valid, and a shifter for sending the valid data to an operation unit in accordance with the mark stored in the mark bit stack.

Abstract: A data processing system capable of implementing at high speeds animating image generation processing and animating image display processing in synchronization with each other, thereby generating and displaying an animating image in a real time. The data processing system uses a given memory area of a storage unit as a screen buffer memory for storing an animating image data for each screen and is provided with an image processor for writing an animating image data for each screen in a screen buffer memory, an image display processor for reading the animating image data for from the screen buffer memory and for generating a display screen graphic signal to be supplied to a display unit and a hardware register circuit having a screen read-out control register corresponding to the animating image data for each screen of the screen buffer memory.

Abstract: A method and apparatus for extending an address space for a vector processor including a vector processing unit and a scalar processing unit. A main storage and an extended storage are also disclosed. An address translator is provided for each requestor within the vector processing unit. Each address translator includes registers for storing main storage addresses and extended storage addresses for the address translation, a register for storing information such as an invalid bit regarding an address space present on the main storage, a register for storing information such as a protection bit representative of an address translation enabled area, and registers for storing a reference bit and a write bit representative of the main storage reference status. The scalar processing unit includes an access controller for allowing a write/pad operation relative to the respective registers in the address translator.

Abstract: A vector processor having a scalar procesing unit, a vector processing unit, a main storage unit, an extended storage unit, a storage control unit, and a paging processor unit, in which the storage control unit address translation for an access request from the vector processing unit to the main storage unit and includes a circuit for storing a kind of an access request issued for each storage location of the main storage the paging processor unit includes a circuit operative in response to issuance of an access request for data in a logical address space not existing in the main storage unit for interrupting a vector access request related thereto from the vector processing unit, a circuit for releasing the interruption according to an instruction, a circuit for loading the main storage unit with requested data of a logical address space existing in the extended storage unit, and a circuit for detecting an area of the main storage having a lower access frequency so as to move data from the area into the exte

Abstract: A vector processing system having a main storage, a vector processor, a scalar processor, and an address translation mechanism in each processor in which data is stored in the main processor.

Abstract: A parallel processor system comprises a main storage, a processor array control apparatus, a control processor which requests the processor array control apparatus to execute the processing in accordance with a procedure start instruction, and a plurality of processor elements each containing a local memory. In response to a designation from the control processor, the processor array control apparatus transfers the program from the main storage to the local memories in all of the processor elements before they are driven. The processor array control apparatus then controls the conditions of the processor elements and drives those processor elements which are capable of processing the procedure in accordance with the procedure start instruction from the control processor.

Abstract: A vector processor has a plurality of vector processing units each of which is connected to main storage via a plurality of memory port logic units. Each of the vector processing units has a resource management circuit, thereby managing its resources and the plurality of memory port logic units as resources and reporting information of the memory port logic unit determined to be used to other vector processing units. The plurality of memory port logic units are thus shared by the plurality of vector processing units.

Abstract: A vector processing apparatus includes a scalar processor for executing scalar instructions and a vector processor for executing vector instructions. The vector processing apparatus has status code registers (SCR) which can be referred to by both processors through a wait managing circuit. The scalar instructions each have an order assurance instruction to assure an order of execution, and the order assurance instruction and the vector instruction each have a field to designate an SCR. The wait managing circuit renders the execution of the instruction in the scalar processor or the vector processor to wait or enable in accordance with a set status or a reset status of the SCR designated by the instruction field, and sets or resets the SCR designated by the instruction field in response to the completion of execution of the instruction to control synchronization of the execution of instructions in both processors.

Abstract: There is provided a vector processor based on a pipeline control method in which a cyclic operation is divided into a plurality of stages and processed. This processor comprises a vector register controller for dividing an operating process into a plurality of fundamental process units and controlling these units, and a phase generator for allowing the vector register controller to time-sharingly make the vector processor operative. This vector processor reads out data from vector registers in which vector elements are stored, operates this data and writes the result of operation into the vector register. With this vector processor, a cyclic operation can be processed in parallel at a high speed without causing a remarkable increase in hardware.