Patents by Inventor Tomoo Hishida
Tomoo Hishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11974439Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: November 21, 2022Date of Patent: April 30, 2024Assignee: KIOXIA CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
-
Publication number: 20230088310Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: November 21, 2022Publication date: March 23, 2023Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
-
Patent number: 11552095Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: March 26, 2021Date of Patent: January 10, 2023Assignee: KIOXIA CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
-
Publication number: 20210375923Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.Type: ApplicationFiled: August 10, 2021Publication date: December 2, 2021Applicant: Kioxia CorporationInventors: Tomoo HISHIDA, Yoshihisa IWATA
-
Publication number: 20210217755Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: March 26, 2021Publication date: July 15, 2021Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
-
Patent number: 10971511Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: March 11, 2020Date of Patent: April 6, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
-
Publication number: 20200212053Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: March 11, 2020Publication date: July 2, 2020Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
-
Patent number: 10622372Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: January 30, 2019Date of Patent: April 14, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
-
Publication number: 20200091190Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.Type: ApplicationFiled: November 25, 2019Publication date: March 19, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Yoshihisa Iwata
-
Patent number: 10586806Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.Type: GrantFiled: July 27, 2018Date of Patent: March 10, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Yoshihisa Iwata
-
Publication number: 20190164979Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: January 30, 2019Publication date: May 30, 2019Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
-
Patent number: 10199387Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: August 17, 2018Date of Patent: February 5, 2019Assignee: Toshiba Memory CorporationInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
-
Publication number: 20180358368Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: August 17, 2018Publication date: December 13, 2018Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
-
Publication number: 20180337194Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.Type: ApplicationFiled: July 27, 2018Publication date: November 22, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tomoo HISHIDA, Yoshihisa IWATA
-
Patent number: 10068916Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.Type: GrantFiled: December 22, 2016Date of Patent: September 4, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Yoshihisa Iwata
-
Patent number: 10056403Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: September 18, 2017Date of Patent: August 21, 2018Assignee: Toshiba Memory CorporationInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
-
Publication number: 20180006042Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: September 18, 2017Publication date: January 4, 2018Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
-
Patent number: 9768188Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: November 11, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
-
Publication number: 20170104002Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoo HISHIDA, Yoshihisa IWATA
-
Publication number: 20170062441Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: November 11, 2016Publication date: March 2, 2017Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE