Patents by Inventor Tomoo Nakayama
Tomoo Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230387219Abstract: A method of manufacturing a semiconductor device includes: forming a silicon oxide film covering each of a first main surface and a second main surface of a semiconductor substrate; forming a redistribution wiring on the first main surface side of the semiconductor substrate; and grinding the second main surface of the semiconductor substrate. This grinding step is performed in a state in which a thickness of the silicon oxide film positioned on the second main surface is equal to or larger than 10 nm and equal to or smaller than 30 nm.Type: ApplicationFiled: March 16, 2023Publication date: November 30, 2023Inventors: Futoshi KOMATSU, Tomoo NAKAYAMA, Katsuhiro UCHIMURA, Hiroshi INAGAWA
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Patent number: 11262500Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.Type: GrantFiled: December 2, 2019Date of Patent: March 1, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tetsuya Iida, Yasutaka Nakashiba, Seigo Namioka, Tomoo Nakayama
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Publication number: 20210184054Abstract: A gallium oxide diode includes: a gallium oxide substrate having an n-type gallium oxide drift layer; an anode electrode of a metal film formed over a front surface of the n-type gallium oxide drift layer; a cathode electrode formed over a rear surface of the gallium oxide substrate; and a reaction layer of a metal oxide film of p-type conductivity formed between the anode electrode and the n-type gallium oxide drift layer. Further, a manufacturing method of a gallium oxide diode includes steps of forming an anode electrode of a metal film over an n-type gallium oxide drift layer formed over a gallium oxide substrate; and forming a reaction layer between the anode electrode and the n-type gallium oxide drift layer by performing a heat treatment to the gallium oxide substrate after forming the anode electrode, the reaction layer being made of a metal oxide film with p-type conductivity.Type: ApplicationFiled: November 18, 2020Publication date: June 17, 2021Inventors: Hironobu MIYAMOTO, Masami SAWADA, Tatsuya USAMI, Tomoo NAKAYAMA
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Publication number: 20210165160Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.Type: ApplicationFiled: December 2, 2019Publication date: June 3, 2021Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA, Seigo NAMIOKA, Tomoo NAKAYAMA
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Patent number: 10818813Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.Type: GrantFiled: November 13, 2018Date of Patent: October 27, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tomoo Nakayama, Shinichi Watanuki, Futoshi Komatsu, Teruhiro Kuwajima, Takashi Ogura, Hiroyuki Okuaki, Shigeaki Shimizu
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Patent number: 10714330Abstract: The reliability of a semiconductor device is improved. A photoresist pattern is formed over a semiconductor substrate. Then, over the semiconductor substrate, a protective film is formed in such a manner as to cover the photoresist pattern. Then, with the photoresist pattern covered with the protective film, an impurity is ion implanted into the semiconductor substrate. Thereafter, the protective film is removed by wet etching, and then, the photoresist pattern is removed.Type: GrantFiled: March 23, 2018Date of Patent: July 14, 2020Assignee: Renesas Electronics CorporationInventors: Tomoo Nakayama, Tatsuya Usami
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Patent number: 10553734Abstract: An improvement is achieved in the reliability of a semiconductor device. Over an insulating layer, an optical waveguide and a p-type semiconductor portion are formed. Over the p-type semiconductor portion, a multi-layer body including an n-type semiconductor portion and a cap layer is formed. Over a first interlayer insulating film covering the optical waveguide, the p-type semiconductor portion, and the multi-layer body, a heater located over the optical waveguide is formed. In the first interlayer insulating film, first and second contact holes are formed. A first contact portion electrically coupled with the p-type semiconductor portion is formed continuously in the first contact hole and over the first interlayer insulating film. A second contact portion electrically coupled with the cap layer is formed continuously in the second contact hole and over the first interlayer insulating film.Type: GrantFiled: May 15, 2018Date of Patent: February 4, 2020Assignee: Renesas Electronics CorporationInventors: Teruhiro Kuwajima, Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama
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Patent number: 10355161Abstract: To achieve a high-reliability germanium photoreceiver. A photoreceiver portion of a germanium photoreceiver comprised of a p type silicon core layer, an i type germanium layer, and an n type silicon layer is covered with a second insulating film and from a coupling hole formed in the second insulating film, a portion of the upper surface of the photoreceiver portion is exposed. The coupling hole has, on the inner wall thereof, a barrier metal film and the barrier metal film has thereon a first-layer wiring made of a tungsten film. Tungsten hardly diffuses from the tungsten film into the i type germanium layer even when a thermal stress is applied, making it possible to prevent the resulting germanium photoreceiver from having diode characteristics deteriorated by the thermal stress.Type: GrantFiled: September 13, 2017Date of Patent: July 16, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Teruhiro Kuwajima, Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama
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Publication number: 20190198703Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.Type: ApplicationFiled: November 13, 2018Publication date: June 27, 2019Inventors: Tomoo NAKAYAMA, Shinichi WATANUKI, Futoshi KOMATSU, Teruhiro KUWAJIMA, Takashi OGURA, Hiroyuki OKUAKI, Shigeaki SHIMIZU
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Patent number: 10211352Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.Type: GrantFiled: October 30, 2017Date of Patent: February 19, 2019Assignee: Renesas Electronics CorporationInventors: Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama, Takashi Ogura, Teruhiro Kuwajima
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Publication number: 20190006535Abstract: An improvement is achieved in the reliability of a semiconductor device. Over an insulating layer, an optical waveguide and a p-type semiconductor portion are formed. Over the p-type semiconductor portion, a multi-layer body including an n-type semiconductor portion and a cap layer is formed. Over a first interlayer insulating film covering the optical waveguide, the p-type semiconductor portion, and the multi-layer body, a heater located over the optical waveguide is formed. In the first interlayer insulating film, first and second contact holes are formed. A first contact portion electrically coupled with the p-type semiconductor portion is formed continuously in the first contact hole and over the first interlayer insulating film. A second contact portion electrically coupled with the cap layer is formed continuously in the second contact hole and over the first interlayer insulating film.Type: ApplicationFiled: May 15, 2018Publication date: January 3, 2019Inventors: Teruhiro KUWAJIMA, Shinichi WATANUKI, Futoshi KOMATSU, Tomoo NAKAYAMA
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Publication number: 20180366321Abstract: The reliability of a semiconductor device is improved. A photoresist pattern is formed over a semiconductor substrate. Then, over the semiconductor substrate, a protective film is formed in such a manner as to cover the photoresist pattern. Then, with the photoresist pattern covered with the protective film, an impurity is ion implanted into the semiconductor substrate. Thereafter, the protective film is removed by wet etching, and then, the photoresist pattern is removed.Type: ApplicationFiled: March 23, 2018Publication date: December 20, 2018Inventors: Tomoo NAKAYAMA, Tatsuya USAMI
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Patent number: 10121927Abstract: A provided semiconductor device includes a Ge photodiode having proper diode characteristics. A groove is provided on a germanium growth protective film, a p-type silicon layer, and a first insulating film from the top surface of the germanium growth protective film without reaching the major surface of a semiconductor substrate. An i-type germanium layer and an n-type germanium layer are embedded in the groove with a seed layer interposed between the layers and the groove, the seed layer being made of amorphous silicon, polysilicon, or silicon germanium. The i-type germanium layer and the n-type germanium layer do not protrude from the top surface of the germanium growth protective film, thereby forming a flat second insulating film having a substantially even thickness on the n-type germanium layer and the germanium growth protective film.Type: GrantFiled: July 21, 2017Date of Patent: November 6, 2018Assignee: Renesas Electronics CorporationInventor: Tomoo Nakayama
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Patent number: 10084078Abstract: In a semiconductor device using a nitride semiconductor, a MISFET is prevented from having deteriorated controllability which will otherwise occur when a tungsten film, which configures a gate electrode of the MISFET, has a tensile stress. A gate electrode of a MISFET having an AlGN/GaN heterojunction is formed from a tungsten film having grains with a relatively small grain size and having no tensile stress. The grain size of the grains of the tungsten film is smaller than that of the grains of a barrier metal film configuring the gate electrode and formed below the tungsten film.Type: GrantFiled: November 25, 2016Date of Patent: September 25, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tomoo Nakayama, Hiroshi Kawaguchi
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Publication number: 20180138325Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.Type: ApplicationFiled: October 30, 2017Publication date: May 17, 2018Applicant: Renesas Electronics CorporationInventors: Shinichi WATANUKI, Futoshi KOMATSU, Tomoo NAKAYAMA, Takashi OGURA, Teruhiro KUWAJIMA
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Publication number: 20180090636Abstract: A provided semiconductor device includes a Ge photodiode having proper diode characteristics. A groove is provided on a germanium growth protective film, a p-type silicon layer, and a first insulating film from the top surface of the germanium growth protective film without reaching the major surface of a semiconductor substrate. An i-type germanium layer and an n-type germanium layer are embedded in the groove with a seed layer interposed between the layers and the groove, the seed layer being made of amorphous silicon, polysilicon, or silicon germanium. The i-type germanium layer and the n-type germanium layer do not protrude from the top surface of the germanium growth protective film, thereby forming a flat second insulating film having a substantially even thickness on the n-type germanium layer and the germanium growth protective film.Type: ApplicationFiled: July 21, 2017Publication date: March 29, 2018Inventor: Tomoo NAKAYAMA
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Publication number: 20180083154Abstract: To achieve a high-reliability germanium photoreceiver. A photoreceiver portion of a germanium photoreceiver comprised of a p type silicon core layer, an i type germanium layer, and an n type silicon layer is covered with a second insulating film and from a coupling hole formed in the second insulating film, a portion of the upper surface of the photoreceiver portion is exposed. The coupling hole has, on the inner wall thereof, a barrier metal film and the barrier metal film has thereon a first-layer wiring made of a tungsten film. Tungsten hardly diffuses from the tungsten film into the i type germanium layer even when a thermal stress is applied, making it possible to prevent the resulting germanium photoreceiver from having diode characteristics deteriorated by the thermal stress.Type: ApplicationFiled: September 13, 2017Publication date: March 22, 2018Inventors: Teruhiro KUWAJIMA, Shinichi WATANUKI, Futoshi KOMATSU, Tomoo NAKAYAMA
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Publication number: 20170170306Abstract: In a semiconductor device using a nitride semiconductor, a MISFET is prevented from having deteriorated controllability which will otherwise occur when a tungsten film, which configures a gate electrode of the MISFET, has a tensile stress. A gate electrode of a MISFET having an AlGN/GaN heterojunction is formed from a tungsten film having grains with a relatively small grain size and having no tensile stress. The grain size of the grains of the tungsten film is smaller than that of the grains of a barrier metal film configuring the gate electrode and formed below the tungsten film.Type: ApplicationFiled: November 25, 2016Publication date: June 15, 2017Inventors: Tomoo NAKAYAMA, Hiroshi KAWAGUCHI
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Patent number: 9589954Abstract: Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.Type: GrantFiled: August 5, 2015Date of Patent: March 7, 2017Assignee: Renesas Electronics CorporationInventors: Akira Mitsuiki, Tomoo Nakayama, Shigeaki Shimizu, Hiroyuki Okuaki
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Publication number: 20160056233Abstract: Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.Type: ApplicationFiled: August 5, 2015Publication date: February 25, 2016Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Akira MITSUIKI, Tomoo NAKAYAMA, Shigeaki SHIMIZU, Hiroyuki OKUAKI