Patents by Inventor Tomoya Nishi

Tomoya Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230234107
    Abstract: A substrate cleaning method and a substrate cleaning apparatus are provided. The substrate cleaning method includes a first step of applying a chemical solution to a lower surface of a substrate, and a second step of subsequently applying a bubble-containing liquid to the lower surface of the substrate.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 27, 2023
    Applicant: Ebara Corporation
    Inventors: NAOYUKI HANDA, Satomi Hamada, Tomoya Nishi
  • Publication number: 20130155042
    Abstract: An image correction data generating system for a display panel that uses unpolished glass is equipped with a signal generator, an imager, and a controller. The signal generator supplies the display panel with a signal for causing that display panel to output an image. The imager captures an output image. The imager is able to resolve an area smaller than the individual pixel sizes of a plurality of pixels. The controller is equipped with an instructing unit, an image acquirer, a high-pass filter, and a correction data generator. The instructing unit outputs instructions for supplying a signal value shared across the entire surface of the display panel to the signal generator. The image acquirer acquires output image data from the imager. The high-pass filter computes high-pass data by applying high-pass filtering to the output image data. The correction data generator outputs an image correction table corresponding to the high-pass data.
    Type: Application
    Filed: January 31, 2011
    Publication date: June 20, 2013
    Applicant: IIX INC.
    Inventors: Shigeharu Ishikawa, Tomoya Nishi
  • Patent number: 5268769
    Abstract: An image signal decoding system for decoding a variable length image data compressed by a modified Huffman code. The decoding object data is cut by a fixed length of 13 bits and the cut data is decoded by using a decode-encode circuit for decoding the input of the modified Huffman code with its end portion equalized and for encoding and generating the code length, the code kind and the run-length number on the basis of the decoded contents, and by using a rotator for shifting the bit data. For decoding a code which immediately follows, the data is shifted with the rotator by the bit number of the code length of the decoding output result, the end portion of the next decoding output result, the end portion of the next decoding object data is equalized with the input end portion of the encode-decode circuit, and it is placed after the immediately following decoding object data and is then input into the decode-encode circuit and decoded.
    Type: Grant
    Filed: August 1, 1991
    Date of Patent: December 7, 1993
    Assignees: Hitachi, Ltd., Hitachi Information Network Ltd., Hitachi Computer Engineering Co., Ltd.
    Inventors: Tadashi Tsuchiya, Hiroo Fujisaki, Tomoya Nishi, Hiromichi Murakami
  • Patent number: 4803653
    Abstract: A memory control system connects, by a single memory bus, plural memories that are individually operable and plural memory access source units so as to effectively use the single memory bus. The memory control system includes a memory request acceptance unit that permits each memory access source unit access to the memories on the basis of the type of access request from each memory access source unit and the type of access request in the memory that is in operation.
    Type: Grant
    Filed: August 6, 1986
    Date of Patent: February 7, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Suzuki, Toshiyuki Takagi, Tomoya Nishi
  • Patent number: 4707153
    Abstract: The line size of character lines constituting a page of print paper is compared with the limited line size. If a line has its line size larger than the limited line size, it is divided into several lines having a smaller line size. An edit control circuit appends a divisional character code to each divided portion of a character which is divided into several lines. An expansion control circuit receives a divisional character code, extracts the divided portion of the character from the patterns of available characters and writes it into a line buffer memory. Patterns in the line buffer memory are written sequentially into a page memory which stores patterns of characters printed in a page of print paper.
    Type: Grant
    Filed: September 17, 1986
    Date of Patent: November 17, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Tomoya Nishi, Mitsuhiro Amari, Kenji Suzuki
  • Patent number: RE34282
    Abstract: A memory control system connects, by a single memory bus, plural memories that are individually operable and plural memory access source units so as to effectively use the single memory bus. The memory control system includes a memory request acceptance unit that permits each memory access source unit access to the memories on the basis of the type of access request from each memory access source unit and the type of access request in the memory that is in operation.
    Type: Grant
    Filed: July 26, 1991
    Date of Patent: June 15, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Suzuki, Toshiyuki Takagi, Tomoya Nishi