Patents by Inventor Tomoyo Maruyama

Tomoyo Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and manufacturing method therefor
    Publication number: 20060151206
    Abstract: A semiconductor device of the present invention includes a semiconductor elements on a circuit board of the semiconductor device, interposing an adhesive material between the semiconductor element and the circuit board. Further, a connection use circuit board including an external terminal connecting portion is mounted on an upper surface of the semiconductor element, interposing an adhesive material between the connection use circuit board and the semiconductor element, and a lower surface of the connection use circuit board and the upper surface of the circuit board are connected with each other via an electrically conductive terminal. A space between the circuit board and the connection use circuit board is sealed with sealing resin.
    Type: Application
    Filed: January 4, 2006
    Publication date: July 13, 2006
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tomoyo Maruyama, Yuji Yano
  • Semiconductor device having a plurality of semiconductor chips
    Patent number: 6181002
    Abstract: A semiconductor device includes an insulative substrate having a layer of interconnection patterns formed on a chip-side surface and external terminals formed on the opposite surface, and a plurality of semiconductor chips stacked on the chip-side surface of the insulative substrate. In the semiconductor device, among the plurality of semiconductor chips, a semiconductor chip having the largest plan surface area has the greatest thickness.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: January 30, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroyuki Juso, Yoshiki Sota, Tomoyo Maruyama
  • Semiconductor device including a wire pattern for relaying connection between a semiconductor chip and leads
    Patent number: 6104084
    Abstract: An insulation material and a wire pattern are provided on at least one of the surfaces of a die pad. Wires of the wire pattern are patterned in such a manner that at least one inner lead included in at least one of two lead groups is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the lead group including the above particular inner lead, while at least one inner lead included in the other lead group is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the other lead group. Accordingly, a multichip-1-package semiconductor device using any kind of semiconductor chip can be realized. Also, the costs of the semiconductor device are saved and the semiconductor device can be developed in a shorter period by omitting the design modification of the semiconductor chip.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: August 15, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiya Ishio, Hiroyuki Nakanishi, Tomoyo Maruyama, Katsunobu Mori, Katsuyuki Tarui