Patents by Inventor Tomoyuki Aoki

Tomoyuki Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230257540
    Abstract: A resin sheet according to the present disclosure includes an uncured product or semi-cured product of a thermosetting resin composition. A melt viscosity of the resin sheet is equal to or greater than 10 Pa·s and equal to or less than 2000 Pa·s when measured using a Koka flow tester under a measuring condition including 130° C. and 1 MPa and is equal to or greater than 6 Pa·s and equal to or less than 1200 Pa·s when measured using the Koka flow tester under a measuring condition including 130° C. and 4 MPa.
    Type: Application
    Filed: July 7, 2021
    Publication date: August 17, 2023
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tomoyuki AOKI, Akihiro YAMAUCHI, Eiichiro SAITO
  • Publication number: 20230101791
    Abstract: A thermosetting resin composition contains an ethylene-propylene-diene copolymer (A), a terminal-modified polyphenylene ether compound (B), an inorganic filler (C), a styrene-based elastomer (D), and a fibrous filler (E).
    Type: Application
    Filed: February 15, 2021
    Publication date: March 30, 2023
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kouichi AOKI, Tomoyuki AOKI
  • Publication number: 20220098404
    Abstract: The thermosetting resin composition contains a radical polymerizable unsaturated compound and an organic radical compound.
    Type: Application
    Filed: January 30, 2020
    Publication date: March 31, 2022
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kouichi AOKI, Tomoyuki AOKI, Eiichiro SAITO
  • Patent number: 10568201
    Abstract: A multilayer printed wiring board has excellent high-frequency characteristics. The multilayer printed wiring board includes one or more conductive layers and one or more insulating layers. In the multilayer printed wiring board, the one or more conductive layers and the one or more insulating layers are alternately stacked. Each insulating layer of the one or more insulating layers includes one or more of a polyolefin resin layer, a fluororesin layer, a polyphenylene ether resin layer, a polyamideimide resin layer, and a polyimide resin layer. At least one insulating layer of the one or more insulating layers includes a polyolefin resin layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 18, 2020
    Assignees: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., TOMOEGAWA CO., LTD.
    Inventors: Hiroaki Takahashi, Tomoyuki Aoki, Kiyotaka Komori, Jun Tochihira, Ryu Harada
  • Publication number: 20180376579
    Abstract: A multilayer printed wiring board has excellent high-frequency characteristics. The multilayer printed wiring board includes one or more conductive layers and one or more insulating layers. In the multilayer printed wiring board, the one or more conductive layers and the one or more insulating layers are alternately stacked. Each insulating layer of the one or more insulating layers includes one or more of a polyolefin resin layer, a fluororesin layer, a polyphenylene ether resin layer, a polyamideimide resin layer, and a polyimide resin layer. At least one insulating layer of the one or more insulating layers includes a polyolefin resin layer.
    Type: Application
    Filed: January 24, 2017
    Publication date: December 27, 2018
    Applicants: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., TOMOEGAWA CO., LTD.
    Inventors: Hiroaki TAKAHASHI, Tomoyuki AOKI, Kiyotaka KOMORI, Jun TOCHIHIRA, Ryu HARADA
  • Patent number: 9508619
    Abstract: A separation layer and a semiconductor element layer including a thin film transistor are formed. A conductive resin electrically connected to the semiconductor element layer is formed. A first sealing layer including a fiber and an organic resin layer is formed over the semiconductor element layer and the conductive resin. A groove is formed in the first sealing layer, the semiconductor element layer, and the separation layer. A liquid is dropped into the groove to separate the separation layer and the semiconductor element layer. The first sealing layer over the conductive resin is removed to form an opening. A set of the first sealing layer and the semiconductor element layer is divided into a chip. The chip is bonded to an antenna formed over a base material. A second sealing layer including a fiber and an organic resin layer is formed so as to cover the antenna and the chip.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: November 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Takuya Tsurume, Hiroki Adachi, Nozomi Horikoshi, Hisashi Ohtani
  • Patent number: 9284410
    Abstract: A method of producing a polyamide includes (i) polycondensating a polyamide precursor containing a salt made from a dicarboxylic acid and a diamine under pressure in a pre-polymerization tank to obtain a prepolymer, and (ii) highly polymerizing the prepolymer with an extruder, wherein when the prepolymer in a molten state which is obtained in the step (i) is fed, by a pump, to the low-pressure extruder from the pre-polymerization tank through a discharge side pipe disposed downstream of the pump, the prepolymer is fed such that the length L [cm] of the discharge side pipe and the linear velocity of discharge v [cm/s] of the prepolymer by the pump satisfy the relationship expressed by the equation, 0.1 [s]?L/v<10 [s].
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: March 15, 2016
    Assignee: Toray Industries, Inc.
    Inventors: Taku Ishimaru, Katsumi Akaike, Daisuke Kikuno, Tomoyuki Aoki, Minoru Noda, Yasunori Tsuda
  • Patent number: 9155204
    Abstract: A manufacturing method of a wiring board and a semiconductor device at low cost and by a simple process, without performing complicated steps many times is proposed. Furthermore, a manufacturing method of a wiring board at low cost and with fewer adverse effects on the environment, and a manufacturing method of a semiconductor device using the wiring board are proposed. A pattern of a conductive material is formed over a first substrate, a conductive film is formed over the pattern by an electrolytic plating process, the pattern and the conductive film are separated, an IC chip including at least one thin film transistor is formed over a second substrate, and the conductive film is electrically connected to the IC chip.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: October 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junya Maruyama, Tomoyuki Aoki
  • Patent number: 9111195
    Abstract: In an antenna and a semiconductor device including the antenna, an object is to reduce the distance between electrodes of a capacitor as much as possible, reduce the area of the electrode of the capacitor as much as possible, and prevent the suppression of response sensitivity and a response range of the semiconductor device. The present invention relates to an antenna including an antenna coil provided over a first region of a base and a capacitor which uses a second region of the base as a dielectric body and which has electrodes provided for opposite planes of the second region of the base, wherein the second region of the base is thinner than the first region of the base, and also relates to a semiconductor device including the antenna.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: August 18, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Susumu Sekiguchi, Shingo Eguchi
  • Publication number: 20150158977
    Abstract: A method of producing a polyamide includes (i) polycondensating a polyamide precursor containing a salt made from a dicarboxylic acid and a diamine under pressure in a pre-polymerization tank to obtain a prepolymer, and (ii) highly polymerizing the prepolymer with an extruder, wherein when the prepolymer in a molten state which is obtained in the step (i) is fed, by a pump, to the low-pressure extruder from the pre-polymerization tank through a discharge side pipe disposed downstream of the pump, the prepolymer is fed such that the length L [cm] of the discharge side pipe and the linear velocity of discharge v [cm/s] of the prepolymer by the pump satisfy the relationship expressed by the equation, 0.1 [s]?L/v<10 [s].
    Type: Application
    Filed: June 19, 2012
    Publication date: June 11, 2015
    Applicant: TORAY INDUSTRIES, INC.
    Inventors: Taku Ishimaru, Katsumi Akaike, Daisuke Kikuno, Tomoyuki Aoki, Minoru Noda, Yasunori Tsuda
  • Patent number: 8648439
    Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: February 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Dozen, Tomoyuki Aoki, Hidekazu Takahashi, Daiki Yamada, Eiji Sugiyama, Kaori Ogita, Naoto Kusumoto
  • Patent number: 8642899
    Abstract: A method for manufacturing an electronic device comprising a terminal provided with a conductor which penetrates a cured prepreg is provided. At least one opening is formed in the prepreg. The prepreg is attached to a substrate over which an electronic element is formed so that the conductor included in the terminal overlaps with the opening. A conductive paste is provided in a region of the prepreg where the opening is provided. Part of the conductive paste flows into the opening to be in contact with the conductor included in the terminal. Then, heat treatment is performed so that the conductive paste and the prepreg are cured. In the process for manufacturing the terminal, it is not necessary to perform a step of forming an opening with a laser beam after the prepreg is cured. Thus, an adverse effect of a laser beam on the electronic element can be eliminated.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshiji Hamatani, Tomoyuki Aoki, Hiroki Adachi, Hiroyuki Yajima
  • Publication number: 20130313329
    Abstract: In an antenna and a semiconductor device including the antenna, an object is to reduce the distance between electrodes of a capacitor as much as possible, reduce the area of the electrode of the capacitor as much as possible, and prevent the suppression of response sensitivity and a response range of the semiconductor device. The present invention relates to an antenna including an antenna coil provided over a first region of a base and a capacitor which uses a second region of the base as a dielectric body and which has electrodes provided for opposite planes of the second region of the base, wherein the second region of the base is thinner than the first region of the base, and also relates to a semiconductor device including the antenna.
    Type: Application
    Filed: August 5, 2013
    Publication date: November 28, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki AOKI, Susumu SEKIGUCHI, Shingo EGUCHI
  • Publication number: 20130270720
    Abstract: A separation layer and a semiconductor element layer including a thin film transistor are formed. A conductive resin electrically connected to the semiconductor element layer is formed. A first sealing layer including a fiber and an organic resin layer is formed over the semiconductor element layer and the conductive resin. A groove is formed in the first sealing layer, the semiconductor element layer, and the separation layer. A liquid is dropped into the groove to separate the separation layer and the semiconductor element layer. The first sealing layer over the conductive resin is removed to form an opening. A set of the first sealing layer and the semiconductor element layer is divided into a chip. The chip is bonded to an antenna formed over a base material. A second sealing layer including a fiber and an organic resin layer is formed so as to cover the antenna and the chip.
    Type: Application
    Filed: June 7, 2013
    Publication date: October 17, 2013
    Inventors: Tomoyuki AOKI, Takuya TSURUME, Hiroki ADACHI, Nozomi HORIKOSHI, Hisashi OHTANI
  • Patent number: 8528827
    Abstract: In an antenna and a semiconductor device including the antenna, an object is to reduce the distance between electrodes of a capacitor as much as possible, reduce the area of the electrode of the capacitor as much as possible, and prevent the suppression of response sensitivity and a response range of the semiconductor device. The present invention relates to an antenna including an antenna coil provided over a first region of a base and a capacitor which uses a second region of the base as a dielectric body and which has electrodes provided for opposite planes of the second region of the base, wherein the second region of the base is thinner than the first region of the base, and also relates to a semiconductor device including the antenna.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Susumu Sekiguchi, Shingo Eguchi
  • Publication number: 20130228885
    Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.
    Type: Application
    Filed: April 18, 2013
    Publication date: September 5, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka DOZEN, Tomoyuki AOKI, Hidekazu TAKAHASHI, Daiki YAMADA, Eiji SUGIYAMA, Kaori OGITA, Naoto KUSUMOTO
  • Patent number: 8459561
    Abstract: A separation layer and a semiconductor element layer including a thin film transistor are formed. A conductive resin electrically connected to the semiconductor element layer is formed. A first sealing layer including a fiber and an organic resin layer is formed over the semiconductor element layer and the conductive resin. A groove is formed in the first sealing layer, the semiconductor element layer, and the separation layer. A liquid is dropped into the groove to separate the separation layer and the semiconductor element layer. The first sealing layer over the conductive resin is removed to form an opening. A set of the first sealing layer and the semiconductor element layer is divided into a chip. The chip is bonded to an antenna formed over a base material. A second sealing layer including a fiber and an organic resin layer is formed so as to cover the antenna and the chip.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: June 11, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Takuya Tsurume, Hiroki Adachi, Nozomi Horikoshi, Hisashi Ohtani
  • Patent number: 8455753
    Abstract: It is an object of the present invention to minimize an electrode in a solar cell to minimize the solar cell. The present invention provides a method for manufacturing a solar cell comprising the steps of forming a first electrode layer over a substrate, forming a photoelectric conversion layer over the first electrode layer, forming an organic layer over the photoelectric conversion layer, forming an opening reaching the first electrode layer in the photoelectric conversion layer, and forming a second electrode layer by filling the opening with a conductive paste, wherein the organic layer modifies the surface of the photoelectric conversion layer and a contact angle between the conductive paste and the photoelectric conversion becomes greater. According to the present invention, wettability of a photoelectric conversion layer can be decreased by forming an organic layer on a surface of the photoelectric conversion layer. Thereby an electrode layer and an insulating isolation layer can be thinned.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: June 4, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuo Nishi, Tomoyuki Aoki, Toshiyuki Isa, Gen Fujii
  • Patent number: 8436354
    Abstract: It is an object of the present invention to provide a method for forming a layer having functionality including a conductive layer and a colored layer and a flexible substrate having a layer having functionality with a high yield. Further, it is an object of the present invention to provide a method for manufacturing a semiconductor device that is small-sized, thin, and lightweight. After coating a substrate having heat resistance with a silane coupling agent, a layer having functionality is formed. Then, after attaching an adhesive to the layer having functionality, the layer having functionality is peeled from the substrate. Further, after coating a substrate having heat resistance with a silane coupling agent, a layer having functionality is formed. Then, an adhesive is attached to the layer having functionality. Thereafter, the layer having functionality is peeled from the substrate, and a flexible substrate is attached to the layer having functionality.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: May 7, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Takuya Tsurume
  • Patent number: 8432018
    Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: April 30, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Dozen, Tomoyuki Aoki, Hidekazu Takahashi, Daiki Yamada, Eiji Sugiyama, Kaori Ogita, Naoto Kusumoto