Patents by Inventor Tomoyuki Morii

Tomoyuki Morii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963433
    Abstract: The present invention provides an organic electroluminescence device capable of having not only a device lifetime comparable to that of an existing organic electroluminescence device but also a small thickness of smaller than 10 ?m and excellent flexibility. The present invention relates to an organic electroluminescence device having a structure including: an anode; a cathode on a substrate; and a laminate of multiple layers between the anode and the cathode, the device having a thickness of smaller than 10 ?m.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: April 16, 2024
    Assignees: The University of Tokyo, Nippon Hoso Kyokai, Nippon Shokubai Co., Ltd.
    Inventors: Takao Someya, Tomoyuki Yokota, Hirohiko Fukagawa, Takahisa Shimizu, Katsuyuki Morii, Tsuyoshi Goya, Kenji Kuwada
  • Patent number: 9533498
    Abstract: A printing method and a printing device, in which printing quality can be maintained without increasing time necessary for printing even if resolution is enhanced. In the printing method, a reference signal is sent at intervals shorter than a minimum time interval at which an ink head provided with plural nozzles can eject ink, at least two reference signals set longer than the minimum time interval are counted as one count, the ink is ejected every one count, and a print pattern is formed by collectivity of the ejected ink. At least a final one count used to form the print pattern is adjusted so as to be lengthened by one or plural reference signals, and the ink is ejected every one count.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: January 3, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Seiji Goto, Tomoyuki Morii, Futoshi Murakami
  • Publication number: 20150224762
    Abstract: A printing method and a printing device, in which printing quality can be maintained without increasing time necessary for printing even if resolution is enhanced. In the printing method, a reference signal is sent at intervals shorter than a minimum time interval at which an ink head provided with plural nozzles can eject ink, at least two reference signals set longer than the minimum time interval are counted as one count, the ink is ejected every one count, and a print pattern is formed by collectivity of the ejected ink. At least a final one count used to form the print pattern is adjusted so as to be lengthened by one or plural reference signals, and the ink is ejected every one count.
    Type: Application
    Filed: January 28, 2015
    Publication date: August 13, 2015
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Seiji GOTO, Tomoyuki MORII, Futoshi MURAKAMI
  • Patent number: 5847411
    Abstract: A first polysilicon layer is formed on a substrate, and vacancies are introduced into an upper portion of the first polysilicon layer, thereby forming a second polysilicon layer. Then, a third polysilicon layer is formed on the second polysilicon layer. After depositing a silicon oxide film and a polysilicon film for a gate on the third polysilicon layer, these films are made into a pattern, thereby forming a control gate electrode and a gate oxide film. Impurity ions are then implanted, thereby forming source/drain regions. Thus, a channel region including the second polysilicon layer with the vacancies introduced is disposed below the control gate electrode, and hence, the mobility of a carrier in the channel region can be improved. As a result, a device can be operated at a high speed with a low voltage.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: December 8, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tomoyuki Morii
  • Patent number: 5424979
    Abstract: A non-volatile memory cell according to the present invention includes: a semiconductor layer of a first conductivity type having an upper portion; a pair of impurity diffusion regions of a second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the pair of impurity diffusion regions in the upper portion of the semiconductor layer; a gate insulating film provided on the upper portion of the semiconductor layer, having thin portions covering at least part of the pair of impurity diffusion regions and a thick portion covering the channel region; floating gate electrodes provided on the thin portions of the gate insulating film; a control gate electrode provided on the thick portion of the gate insulating film and electrically insulated from the floating gate electrodes; and an insulating film provided between the control gate electrode and the floating gate electrodes, capacity-coupling the control gate electro
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: June 13, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tomoyuki Morii