Abstract: A configuration register update mode can be implemented as a register word update (RWUPD) mode for a registering clock driver (RCD) or as a mode register update (MRUPD) mode for a dynamic random access memory (DRAM) device. In the update mode, In the update mode, the memory device (either the RCD or the DRAM) can perform configuration of any number of configuration registers with in-band register writes. The in-band register writes can be used to configure decision feedback equalization (DFE) settings, as well as other configuration settings for non-DFE configurations of a memory device interface.

Abstract: Decision feedback equalization (DFE) training time in a memory device is reduced through the use of a hybrid search to select values of tap coefficients for taps in the DFE. The hybrid search includes two searches. A first search is performed to identify initial values of tap coefficients, a second search uses the initial values of tap coefficients to find the final values of tap coefficients.

Abstract: An apparatus is described. The apparatus includes data buffer to memory chip write training circuitry. The data buffer to memory chip write training circuitry to send MDQ/MDQS phase relationship programming information, write commands and read commands to the data buffer chips for multiple write training iterations without a host memory controller having provided the MDQ/MDQS phase relationship programming information, the write commands and the read commands to the data buffer to memory chip write training circuitry.

Abstract: An apparatus is described. The apparatus includes a data buffer chip having write leveling training circuitry. The write leveling training circuitry to detect when a sampled value of a WL pulse within a memory chip has changed. Another apparatus is described. The other apparatus includes a registering clock driver (RCD) chip having write leveling training circuitry to determine when to send a write command to a memory chip and a data buffer chip during an external write leveling training process for the memory chip.

Abstract: System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.

Abstract: An apparatus is described. The apparatus includes a register clock redriver (RCD) chip comprising a buffer communication (BCOM) interface, a BCOM training control circuit and BCOM training control register space, the BCOM training control circuit is to: transmit a series of symbol transmissions over the BCOM interface to a data buffer with different respective clock phase delays to sweep the symbol transmissions within an eye window; collect resultants of the symbol transmissions from the data buffer; and, perform an analysis on the resultants to determine an appropriate clock phase within the eye window.

Abstract: Autonomous QCS and QCA training by the RCD can remove host intervention, freeing the host to handle other tasks while the RCD trains the backside CS and CA buses. In one example, the RCD autonomously trains QCS and/or QCA signal lines by triggering the DRAMs entry into a training mode, driving the signal lines with patterns, and sweeping through delay values for the signal lines. The RCD receives training feedback from the DRAMs over a sideband bus (such as an I3C bus) and programs a delay for the one or more signal lines based on the training feedback. Thus, autonomous QCS and QCA training can reduce training time for every boot by removing host intervention and saving hose cycles.

Abstract: A memory chip is described. The memory chip includes self identification circuitry to self identify the memory chip. The self identification circuitry is to determine a resistance of a resistor and correlate the memory chip's identity to the resistance. A registering clock driver (RCD) chip is described. The RCD chip includes a controller. The controller is to receive provisional IDs (PIDs) from memory chips on a same memory module as the RCD chip. The controller is to program the memory chips with respective logical IDs (LIDs) based on a correlation of the PIDs and the LIDs.

Abstract: A differential Data Strobe (DQS) signal is used to transmit and receive Cyclic Redundancy Check (CRC) between a host memory controller and a memory module. The differential DQS strobe signal is trained before it is used for transactions. The training is performed by sending and receiving a CRC pattern on the differential DQS strobe signal between the host memory controller and a buffer in the memory module.