Patents by Inventor Tony Hurson

Tony Hurson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111691
    Abstract: Techniques for time-aware remote data transfers. A time may be associated with a remote direct memory access (RDMA) operation in a translation protection table (TPT). The RDMA operation may be permitted or restricted based on the time in the TPT.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Daniel Christian Biederman, Kenneth Keels, Renuka Vijay Sapkal, Tony Hurson
  • Patent number: 11709774
    Abstract: Examples described herein relates to a network interface apparatus that includes packet processing circuitry and a bus interface. In some examples, the packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write the data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory. In some examples, the packet processing circuitry is to issue a command to an input output (IO) controller to cause the IO controller to write the data to the cache and the non-volatile memory.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: July 25, 2023
    Assignee: Intel Corporation
    Inventors: Ren Wang, Yifan Yuan, Yipeng Wang, Tsung-Yuan C. Tai, Tony Hurson
  • Patent number: 11651092
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: May 16, 2023
    Assignee: INTEL CORPORATION
    Inventors: Brian S. Hausauer, Lokpraveen B. Mosur, Tony Hurson, Patrick Fleming, Adrian R. Pearson
  • Publication number: 20230123387
    Abstract: Examples described herein relate to a network interface device that includes circuitry to cause transmission of a packet following transmission of one or more data packets to a receiver, wherein the packet comprises one or more of: a count of transmitted data, a timestamp of transmission of the packet, and/or an index value to one or more of a count of transmitted data and a timestamp of transmission of the packet. In some examples, the network interface device includes circuitry to receive, from the receiver, a second packet that includes a copy of the count of transmitted data and the timestamp of transmission of the packet or the index from the packet. In some examples, the network interface device includes circuitry to perform congestion control based on the received copy of the count of transmitted data and the timestamp of transmission of the packet.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 20, 2023
    Inventors: Robert SOUTHWORTH, Rong PAN, Tony HURSON, Siqi LIU
  • Patent number: 11621918
    Abstract: A transmitter can manage when a transmit queue is permitted to transmit and an amount of data permitted to be transmitted. After a transmit queue is permitted to transmit, the transmit queue can be placed in a sleep state if the transmit queue has exceeded its permitted data transmission quota. The wake time of the transmit queue can be scheduled based on a token accumulation rate for the transmit queue. The token accumulation rate can be increased if the transmit queue has other data to transmit after the data transmission. The token accumulation rate can be decreased if the transmit does not have other data to transmit.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Ben-Zion Friedman, Simoni Ben-Michael, Arvind Srinivasan, Tony Hurson, Adam Conyers, Hemanth Krishnan
  • Patent number: 11616723
    Abstract: At a network-connected device, congestion at an egress queue can be detected. A potential source of congestion can be identified based on characteristics of a packet that caused the egress queue to become congested. The source of congestion can be a congestion group of transmitters. A group congestion message can be sent to the group of transmitters. The message can identify the packet that caused the egress queue to become congested. Transmitters can respond to the message by reducing their peak transmission rate.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: March 28, 2023
    Assignee: Intel Corporation
    Inventors: Ben-Zion Friedman, Simoni Ben-Michael, Arvind Srinivasan, Tony Hurson, Adam Conyers, Hemanth Krishnan
  • Publication number: 20220114030
    Abstract: Examples described herein relate to a network interface device that includes circuitry to perform operations, offloaded from a host, to identify at least one locator of at least one target storage associated with a storage access command based on operations selected from among multiple available operations, wherein the available operations comprise two or more: entry lookup by the network interface device, hash-based calculation on the network interface device, or control plane processing on the network interface device.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Inventors: Salma Mirza JOHNSON, Jose NIELL, Bradley A. BURRES, Yadong LI, Scott D. PETERSON, Tony HURSON, Sujoy SEN
  • Publication number: 20220103516
    Abstract: An apparatus comprising a first computing platform including a processor to execute a first trusted executed environment (TEE) to host a first plurality of virtual machines and a first network interface controller to establish a trusted communication channel with a second computing platform via an orchestration controller.
    Type: Application
    Filed: December 10, 2021
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Pradeep Pappachan, Luis Kida, Donald E. Wood, Tony Hurson, Reouven Elbaz, Reshma Lal
  • Publication number: 20210359955
    Abstract: Examples described herein relate to a network interface device comprising: a host interface, a direct memory access (DMA) engine, and circuitry to allocate a region in a cache to store a context of a connection. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on connection reliability and wherein connection reliability comprises use of a reliable transport protocol or non-use of a reliable transport protocol. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on expected length of runtime of the connection and the expected length of runtime of the connection is based on a historic average amount of time the context for the connection was stored in the cache. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on content transmitted and the content transmitted comprises congestion messaging payload or acknowledgement.
    Type: Application
    Filed: July 23, 2021
    Publication date: November 18, 2021
    Inventors: Malek MUSLEH, Tony HURSON, Pedro YEBENES SEGURA, Allister ALEMANIA, Roberto PENARANDA CEBRIAN, Ayan BANERJEE, Robert SOUTHWORTH, Sujoy SEN, Curt E. BRUNS
  • Publication number: 20210264042
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.
    Type: Application
    Filed: April 22, 2021
    Publication date: August 26, 2021
    Applicant: INTEL CORPORATION
    Inventors: BRIAN S. HAUSAUER, Lokpraveen B. Mosur, Tony Hurson, Patrick Fleming, Adrian R. Pearson
  • Patent number: 11042657
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to de determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: June 22, 2021
    Assignee: INTEL CORPORATION
    Inventors: Brian S. Hausauer, Lokpraveen B. Mosur, Tony Hurson, Patrick Fleming, Adrian R. Pearson
  • Patent number: 10944660
    Abstract: Examples described herein include configuration of a transmitting network device to identify a source queue-pair identifier in at least some of the packets that are transmitted to an endpoint destination. A network device that receives packets and experiences congestion can determine if a congestion causing packet includes a source queue-pair identifier. If the congestion causing packet includes a source queue-pair identifier, the network device can form and transmit a congestion notification message with a copy of the source queue-pair identifier to the transmitting network device. The transmitting network device can access a context for the congestion causing packet using the source queue-pair identifier without having to perform a lookup to identify the context.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Tony Hurson, Simoni Ben-Michael, Ben-Zion Friedman
  • Publication number: 20200371914
    Abstract: Examples described herein relates to a network interface apparatus that includes packet processing circuitry and a bus interface. In some examples, the packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write the data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory. In some examples, the packet processing circuitry is to issue a command to an input output (IO) controller to cause the IO controller to write the data to the cache and the non-volatile memory.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 26, 2020
    Inventors: Ren WANG, Yifan YUAN, Yipeng WANG, Tsung-Yuan C. TAI, Tony HURSON
  • Publication number: 20190342199
    Abstract: Examples described herein include configuration of a transmitting network device to identify a source queue-pair identifier in at least some of the packets that are transmitted to an endpoint destination. A network device that receives packets and experiences congestion can determine if a congestion causing packet includes a source queue-pair identifier. If the congestion causing packet includes a source queue-pair identifier, the network device can form and transmit a congestion notification message with a copy of the source queue-pair identifier to the transmitting network device. The transmitting network device can access a context for the congestion causing packet using the source queue-pair identifier without having to perform a lookup to identify the context.
    Type: Application
    Filed: July 19, 2019
    Publication date: November 7, 2019
    Inventors: Tony HURSON, Simoni BEN-MICHAEL, Ben-Zion FRIEDMAN
  • Publication number: 20190116121
    Abstract: A transmitter can manage when a transmit queue is permitted to transmit and an amount of data permitted to be transmitted. After a transmit queue is permitted to transmit, the transmit queue can be placed in a sleep state if the transmit queue has exceeded its permitted data transmission quota. The wake time of the transmit queue can be scheduled based on a token accumulation rate for the transmit queue. The token accumulation rate can be increased if the transmit queue has other data to transmit after the data transmission. The token accumulation rate can be decreased if the transmit does not have other data to transmit.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 18, 2019
    Inventors: Ben-Zion FRIEDMAN, Simoni BEN-MICHAEL, Arvind SRINIVASAN, Tony HURSON, Adam CONYERS, Hemanth KRISHNAN
  • Publication number: 20190116122
    Abstract: At a network-connected device, congestion at an egress queue can be detected. A potential source of congestion can be identified based on characteristics of a packet that caused the egress queue to become congested. The source of congestion can be a congestion group of transmitters. A group congestion message can be sent to the group of transmitters. The message can identify the packet that caused the egress queue to become congested. Transmitters can respond to the message by reducing their peak transmission rate.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 18, 2019
    Inventors: Ben-Zion FRIEDMAN, Simoni BEN-MICHAEL, Arvind SRINIVASAN, Tony HURSON, Adam CONYERS, Hemanth KRISHNAN
  • Publication number: 20190102568
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to de determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.
    Type: Application
    Filed: September 30, 2017
    Publication date: April 4, 2019
    Inventors: BRIAN S. HAUSAUER, LOKPRAVEEN B. MOSUR, TONY HURSON, PATRICK FLEMING, ADRIAN R. PEARSON
  • Patent number: 5128891
    Abstract: An apparatus for performing the division of a first operand by a second operand by iteratively producing a series of partial remainders and predicted quotient bits utilizing the generation of multiples of the second operand and the selection of one of the generated multiples. The second operand is first selected as a first partial remainder. A first quotient bit is predicted from the first and second operands and a next quotient bit is predicted from the partial remainder and the second operand. One of the generated multiples is selected for producing a next partial remainder based upon the next quotient prediction. A next partial remainder is then produced from the produced partial remainder and the selected multiple of the second operand.
    Type: Grant
    Filed: April 2, 1990
    Date of Patent: July 7, 1992
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas W. Lynch, Stephen D. McIntyre, Ken Tseng, Salim A. Shah, Tony Hurson