Abstract: In one embodiment, an apparatus comprises a multi-dimensional memory and a plurality of processing elements to perform a matrix operation, wherein the matrix operation comprises a max pooling operation on one or more matrix operands. The plurality of processing elements comprises one or more matrix processors, and the plurality of processing elements is configured to: receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extract the one or more matrix operands from the matrix data; perform the max pooling operation using the one or more matrix operands; and obtain a result of the max pooling operation.

Abstract: A cache system has a multilevel cache architecture. An L1 cache receives instructions from an external memory. An L0 cache has a first predetermined number L0 of cache lines for receiving instructions from the L1 cache. An assist cache has a victim cache and a prefetch cache. The victim cache stores a second predetermined number VC of cache lines, and the prefetch cache stores a third predetermined number PC of cache lines. The victim cache receives instructions from the L0 cache. The prefetch cache receives instructions from the L1 cache. A victim filter stores a fourth predetermined number VF of addresses wherein VF is a function of L0 and a number of cache writes. The number of cache writes to the L0 and the victim cache is reduced relative to using the L0 cache without the assist cache.

Abstract: A processor having an execution pipeline and a cache memory including a plurality of cache blocks with instruction words held in selected ones of the cache blocks. An ICBI address buffer is provided for holding addresses of instruction cache blocks to be invalidated by ICBI instructions pending in the processor's execution pipeline. An instruction cache controller coupled to the cache memory generates cache accesses to invalidate specified cache blocks in response to receiving buffered addresses from the ICBI address buffer. Preferably the cache accesses serve to commit ICBI instructions to the instruction cache asynchronously with respect to the processor's execution pipeline.