Abstract: An apparatus includes a light source to generate source light through an optically transmissive medium to an object. A receiver includes a near zone light sensor and a far zone light sensor positioned on a substrate with the light source. The near zone light sensor is positioned on the substrate to, in response to the generated source light, receive reflected source light from the object and the optically transmissive medium. The far zone light sensor is positioned on the substrate to, in response to the source light, receive the reflected source light from the object and to receive a reduced quantity of the reflected source light from the optically transmissive medium compared to the near zone light sensor.

Abstract: An apparatus includes a light source to generate source light through an optically transmissive medium to an object. A receiver includes a near zone light sensor and a far zone light sensor positioned on a substrate with the light source. The near zone light sensor is positioned on the substrate to, in response to the generated source light, receive reflected source light from the object and the optically transmissive medium. The far zone light sensor is positioned on the substrate to, in response to the source light, receive the reflected source light from the object and to receive a reduced quantity of the reflected source light from the optically transmissive medium compared to the near zone light sensor.

Abstract: A hot swap controller includes a shunt resistor (32-1,2) and a power transistor (37-1,2) having a source coupled to a load maintains the first power transistor in a fully-turned-on condition to cause it to deliver a load current contribution (IL1,2) which flows through the shunt resistor and the power transistor to the load (25). Current sensing circuitry (35-1,2) produces a first control signal (V45-1,2-V47-1,2) equal to the difference between a DC component (V47-1) proportional to a first load current contribution (IL1) flowing in the first shunt resistor and a feedback-based component (V45-1). A control amplifier (49-1,2) produces a second control signal (V51-1,2) in response to the first control signal to modify a drive signal (53-1) to the power transistor so as to reduce a channel resistance of the power transistor if the first control signal exceeds a predetermined level.

Abstract: Multiplier circuitry includes first multiplier circuit including a first transistor having an emitter coupled to a first conductor, a base coupled to a second conductor, and a collector coupled to a third conductor, a second transistor having an emitter coupled to the first conductor, a base coupled to a fourth conductor, and a collector coupled to a fifth conductor, a third transistor having an emitter coupled to the second conductor and a base and collector coupled to a supply voltage, and a fourth transistor having an emitter coupled to the fourth conductor and a base and collector coupled to the supply voltage. Chopper includes a first switch to provide a chopped differential signal between the second and fourth conductors and a second switch for un-chopping a first differential output signal produced between the third and fifth conductors to provide an un-chopped differential output signal between the third and fifth conductors.

Abstract: Multiplier circuitry includes first multiplier circuit including a first transistor having an emitter coupled to a first conductor, a base coupled to a second conductor, and a collector coupled to a third conductor, a second transistor having an emitter coupled to the first conductor, a base coupled to a fourth conductor, and a collector coupled to a fifth conductor, a third transistor having an emitter coupled to the second conductor and a base and collector coupled to a supply voltage, and a fourth transistor having an emitter coupled to the fourth conductor and a base and collector coupled to the supply voltage. Chopper includes a first switch to provide a chopped differential signal between the second and fourth conductors and a second switch for un-chopping a first differential output signal produced between the third and fifth conductors to provide an un-chopped differential output signal between the third and fifth conductors.

Abstract: A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin?) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (?) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.

Abstract: A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin?) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (?) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.

Abstract: A hot swap controller includes a shunt resistor (32-1,2) and a power transistor (37-1,2) having a source coupled to a load maintains the first power transistor in a fully-turned-on condition to cause it to deliver a load current contribution (I1,2) which flows through the shunt resistor and the power transistor to the load (25). Current sensing circuitry (35-1,2) produces a first control signal (V45-1,2-V47-1,2) equal to the difference between a DC component (V47-1) proportional to a first load current contribution (IL1) flowing in the first shunt resistor and a feedback-based component (V45-1). A control amplifier (49-1,2) produces a second control signal (V51-1,2) in response to the first control signal to modify a drive signal (53-1) to the power transistor so as to reduce a channel resistance of the power transistor if the first control signal exceeds a predetermined level.

Abstract: An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFL), a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFH), a second input signal (Vin?) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C).

Abstract: An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFL), a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFH), a second input signal (Vin?) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C).

Abstract: A bandgap reference circuit as may be used in ultra-low current applications is provided. An exemplary bandgap circuit can be configured to generate a positive temperature coefficient without the need for a resistor to offset a negative temperature coefficient. In accordance with an exemplary embodiment of the present invention, a bandgap circuit comprises a negative temperature coefficient generated from a junction device and a positive temperature coefficient generated from an FET-based device. An exemplary junction device can comprise a bipolar, junction diode or any other device for generating a negative temperature coefficient, while an exemplary FET-based device comprises a gate-drain connected device configured to provide a gate-source voltage having a positive temperature coefficient coupled in series with the bipolar device.

Abstract: A low drop-out (“LDO”) voltage regulator includes an output stage of having a pass device and a discharge device arranged in complementary voltage follower configurations to both source load current to and sink load current from a regulated output voltage conductor. The pass device and the discharge device are controlled through a single feedback loop.

Abstract: An LDO voltage regulator includes an error amplifier having a first input coupled to a first reference voltage, a second input receiving a feedback signal, and an output producing a first control signal. An output transistor has a gate, a drain coupled to an unregulated input voltage, and a source coupled to produce a regulated output voltage on an output conductor. A feedback circuit is coupled between the output conductor and a second reference voltage. An overvoltage comparator has a first input coupled to receive the first reference voltage and a second input coupled to respond to the feedback signal to produce a discharge control signal indicating occurrence of an output overvoltage of at least a predetermined magnitude to control a discharge transistor coupled between the output conductor and the second reference voltage. An output current sensing circuit produces a control current representative of the drain current of the output transistor.

Abstract: A low drop out voltage regulator includes an error amplifier (12) having a first input coupled to a first reference voltage (VREF), a second input receiving a feedback signal, and an output (15) producing an output signal (VAMPOUT). An output transistor (18) has a gate, a drain coupled to an unregulated input voltage (VIN), and a source coupled to produce a regulated output voltage (VOUT) on an output conductor (19). A feedback circuit (20,22) is coupled between the output conductor (19) and a reference voltage (GND) to produce the feedback signal. A capacitor (16) is coupled between the output (15) of the error amplifier and the gate (17) of the output transistor (18). A servo amplifier (24) has a first input coupled to a second reference voltage (VVREF), a second input coupled to the output (15) of the error amplifier. A low current charge pump circuit (26B) supplies an output current into a supply voltage terminal of the servo amplifier.

Abstract: A system for accurately measuring current drawn intermittently by an inductive load over a time interval T including a first and a second time subinterval during which the load is in state S1 and state S2 respectively and drawing current and a third time subinterval during which the load is in state S3, an idle state, and drawing substantially zero current is provided. In a preferred embodiment, the current measuring system includes a pilot current detection circuit having a pulse width modulator which generates a 1/2T.sub.1 timing signal representing the average amplitude of the current drawn by the load while in states S1 and S2. A correction circuit generates a logic signal that indicates the time of transition of the inductive load from state S2 to state S3 and from state S3 to state S1. The logic signal is used to clock a first sample and hold circuit to provide a scaling factor utilized to correct the average load current.

Abstract: An impedance buffer circuit suitable for monolithic implementation as a capacitive load driver such as required in sample-and-hold circuit applications. This impedance buffer circuit provides the speed of the emitter-follower amplifier and the accuracy of the differential amplifier without the normal output offset, excessive overshoot and ringing or slew rate limitations. An emitter-follower amplifier element is coupled to operate in parallel with a differential amplifier element, which may be optimized for performance over the final 0.7 volt (V.sub.be) portion at each end of the output voltage range.

Abstract: A step-up converter is utilized to convert a first lower input voltage to a second higher output voltage. The circuit includes a soft start capability such that ringing due to excessive voltage and current is substantially eliminated. In addition, this converter includes an overcurrent protection mechanism if a load failure or other overcurrent condition occurs.

Abstract: A power amplifier supplies substantial load currents that must be accurately monitored to provide feedback so that the load currents can be properly controlled. A sense current is generated from a load current that is scaled such that the sense current is an accurate representation of the load current but having a substantially smaller magnitude. The scaled sense current is generated by coupling a power sense resistor to a pilot sense resistor by a voltage follower. The power sense resistor is in series with the load current and develops a load voltage thereacross. A sense voltage, being substantially equal to the load voltage is impressed at the pilot sense resistor by the voltage follower. The pilot sense resistor is some predetermined ratio of the power sense resistor so that absolute values are not critical. The sense current flowing through the pilot sense resistor is therefore scaled according to the ratios of the power and pilot sense resistors.

Abstract: The current mode sample-and-hold circuit includes a differential amplifier having a non-inverting input coupled to a first leg of a current mirror from which a first current to be sampled is drawn. An inverting input of the differential amplifier is coupled to its output and further coupled to a capacitor through a sample hold switch. The first current drawn from the first leg of the current mirror causes the capacitor to charge, through the differential amplifier. The charged capacitor is coupled to the current mirror and biases the current mirror so as to provide the required first current. Opening the sample hold switch causes the capacitor to maintain a bias level determined by the first current. The bias signal in turn causes a mirrored current flowing in a second leg of the current mirror to be maintained, even in the absence of the first current. Thus an input current is sampled and a corresponding output current is provided. The capacitor operates in a feedback loop for improving accuracy.

Abstract: An improved MOS switched current mode drive circuit designed for use in systems interfacing multiple peripheral devices with one or more CPU units attached to a 360/370 channel.