Abstract: In a network device, apparatus and methods perform precision time stamping. A time agent receives a master pace signal corresponding to a time representation based on a master real time clock in a master clock domain. A time accumulator accumulates time units one fill quantum at a time based on the master pace signal. The time accumulator decreases the accumulated time units by a leak quantum according to a local clock signal running at a higher frequency than the master pace signal. Correction logic periodically generates, at a granularity corresponding to the frequency of the local clock signal, an updated time representation in a target clock domain based on a residual number of time units in the time accumulator before depositing an additional fill quantum of time units in the time accumulator.

Abstract: In a network device, apparatus and methods perform precision time stamping. A time agent receives a master pace signal corresponding to a time representation based on a master real time clock in a master clock domain. A time accumulator accumulates time units one fill quantum at a time based on the master pace signal. The time accumulator decreases the accumulated time units by a leak quantum according to a local clock signal running at a higher frequency than the master pace signal. Correction logic periodically generates, at a granularity corresponding to the frequency of the local clock signal, an updated time representation in a target clock domain based on a residual number of time units in the time accumulator before depositing an additional fill quantum of time units in the time accumulator.

Abstract: In a network device, apparatus and methods perform precision time stamping. A time agent receives a master pace signal corresponding to a time representation based on a master real time clock in a master clock domain. A time accumulator accumulates time units one fill quantum at a time based on the master pace signal. The time accumulator decreases the accumulated time units by a leak quantum according to a local clock signal running at a higher frequency than the master pace signal. Correction logic periodically generates, at a granularity corresponding to the frequency of the local clock signal, an updated time representation in a target clock domain based on a residual number of time units in the time accumulator before depositing an additional fill quantum of time units in the time accumulator.

Abstract: In a network device, apparatus and methods perform precision time stamping. A time agent receives a master pace signal corresponding to a time representation based on a master real time clock in a master clock domain. A time accumulator accumulates time units one fill quantum at a time based on the master pace signal. The time accumulator decreases the accumulated time units by a leak quantum according to a local clock signal running at a higher frequency than the master pace signal. Correction logic periodically generates, at a granularity corresponding to the frequency of the local clock signal, an updated time representation in a target clock domain based on a residual number of time units in the time accumulator before depositing an additional fill quantum of time units in the time accumulator.

Abstract: The present invention relates to service and maintenance solutions for programmable and/or reconfigurable modules (CM1, . . . , CMn), which are included in the nodes of a communications network (140). The module (CM1) contains a first digital storage unit (M1), which holds information pertaining to the accomplishment of a primary function of the module. A secondary function of the module involves control of the primary function. The module has an optical bi-directional interface (Iw) towards the first digital storage unit. Data in the first digital storage unit may be read out (D0) and may also be updated (Di) by the portable software carrier unit via the optical bi-directional interface. Data read-out as well as data updating may be accomplished independently of the primary function. Preferably, an access module (A) controls the bi-directional interface in response to an authorization signal (SA) from an authorization unit (120, 121, 122, 123).

Abstract: In a differential line receiver circuit having differential amplifier circuit where output rise and fall times are influenced by the ability of internal current sources to charge parasitic capacitances, a feedback circuit is provided to tune those current sources so as to deliver equal rise and fall time on both outputs. According to one embodiment a detector signal is derived from timing errors resulting from such rise and fall time discrepancies by means of a nested CMOS inverter arrangement coupled to an integrating element, and then used to control one or both of said current sources.

Abstract: The present invention relates to service and maintenance solutions for programmable and/or reconfigurable modules (CM1, . . . , CMn), which are included in the nodes of a communications network (140). The module (CM1) contains a first digital storage unit (M1), which holds information pertaining to the accomplishment of a primary function of the module. A secondary function of the module involves control of the primary function. The module has an optical bi-directional interface (Iw) towards the first digital storage unit. Data in the first digital storage unit may be read out (D0) and may also be updated (Di) by the portable software carrier unit via the optical bi-directional interface. Data read-out as well as data updating may be accomplished independently of the primary function. Preferably, an access module (A) controls the bi-directional interface in response to an authorization signal (SA) from an authorization unit (120, 121, 122, 123).

Abstract: A digital logic interface circuit makes use of a logic signal representative of a logic signaling level definition, to determine the logic swing amplitude of signals from a given source adopting the same logic signaling level definition. The digital logic interface circuit generates a threshold level from the logic swing amplitude thus determined, and compares digital logic input signals against the threshold level in order to discriminate different logic levels in the digital logic input signals. The comparison result is provided as digital interface output signals adopting a predetermined logic signaling level definition for use by subsequent system sections. Examples of such representative signals are the digital input logic signals themselves, clock signals or line encoded signals. Other examples can be mode control signals or NRZ signals.

Abstract: A digital logic interface circuit makes use of a logic signal representative of a logic signaling level definition, to determine the logic swing amplitude of signals from a given source adopting the same logic signaling level definition. The digital logic interface circuit generates a threshold level from the logic swing amplitude thus determined, and compares digital logic input signals against the threshold level in order to discriminate different logic levels in the digital logic input signals. The comparison result is provided as digital interface output signals adopting a predetermined logic signaling level definition for use by subsequent system sections. Examples of such representative signals are the digital input logic signals themselves, clock signals or line encoded signals. Other examples can be mode control signals or NRZ signals.

Abstract: In a differential line receiver circuit having differential amplifier circuit where output rise and fall times are influenced by the ability of internal current sources to charge parasitic capacitances, a feedback circuit is provided to tune those current sources so as to deliver equal rise and fall time on both outputs. According to one embodiment a detector signal is derived from timing errors resulting from such rise and fall time discrepancies by means of a nested CMOS inverter arrangement coupled to an integrating element, and then used to control one or both of said current sources.

Abstract: A differential signal transfer circuit to control the common mode level of a differential signal, comprising an input common mode level detection circuit, for detecting the common mode level of an incoming signal, two capacitors coupled between the first input and output and the second input and output respectively, and a control circuit adapted to control an output common mode voltage level at the output terminals by controlling the levels of charge on the two capacitors dependent on the common mode level of the incoming signal as detected by the input common mode detector.

Abstract: A differential signal transfer circuit to control the common mode level of a differential signal, comprising an input common mode level detection circuit (40), for detecting the common mode level of an incoming signal, two capacitors (60, 61) coupled between the first input and output and the second input and output respectively, and a control circuit (50) adapted to control an output common mode voltage level at the output terminals (20, 21) by controlling the levels of charge on the (60, 61) dependent on the common mode level of the incoming signal as detected by the input common mode detector (40).

Abstract: A delay matched clock and data generator utilizes a re-timing element having the functionality of a two-input multiplexer, connected and operated such that the level on the output(s) is controlled from level control inputs, and the timing of transitions on the output(s) is controlled from timing control inputs. The level control inputs on the re-timing element correspond to the data input(s) on an equivalent multiplexer. The generator further has control inputs for stopping the clock low or stopping the clock high, and the generator may be operated for polarity independent clock gating or clock synthesis.

Abstract: A device for monitoring supply voltage locally on integrated circuits after mounting on electronic component boards (11) includes at least one voltage monitor (31) as well as boundary scan means (36, 36', 37) for reading out the result of the monitoring. The monitor includes an extreme value detector (41), situated at the place on the circuit surface where voltage monitoring is desired and detecting the minimum absolute voltage between a local supply voltage lead and a local ground lead. The minimum value detector comprises one or two FET transistors at most.