Patents by Inventor Tore Lennart Kellgren

Tore Lennart Kellgren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methodology for storing and updating on-chip revision level
    Patent number: 8209654
    Abstract: Logic to indicate a revision level includes multiple cells for one bit of the revision level. The cells being wired to be a pass-through cell or a swap cell during fabrication. At least some of the cells are such that to change the bit of the revision level, it is sufficient to change any single mask of a group of masks. The change to the single mask switches at least one of the cells from pass-through cell to a swap cell, or vice-versa.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: June 26, 2012
    Assignee: Exar Corporation
    Inventors: Tore Lennart Kellgren, J. Antonio Salcedo
  • METHODOLOGY FOR STORING AND UPDATING ON-CHIP REVISION LEVEL
    Publication number: 20110185337
    Abstract: Logic to indicate a revision level includes multiple cells for one bit of the revision level. The cells being wired to be a pass-through cell or a swap cell during fabrication. At least some of the cells are such that to change the bit of the revision level, it is sufficient to change any single mask of a group of masks. The change to the single mask switches at least one of the cells from pass-through cell to a swap cell, or vice-versa.
    Type: Application
    Filed: January 22, 2010
    Publication date: July 28, 2011
    Applicant: EXAR CORPORATION
    Inventors: Tore Lennart Kellgren, J. Antonio Salcedo