Patents by Inventor Toru Anezaki
Toru Anezaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7595231Abstract: In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of the MIS transistor in the logic area are made of silicon oxide. A semiconductor device of logic-memory can be manufactured by a reduced number of manufacture processes while the transistor characteristics are stabilized and the fine patterns in the memory cell are ensured.Type: GrantFiled: November 14, 2006Date of Patent: September 29, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Toshio Taniguchi, Taiji Ema, Toru Anezaki
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Publication number: 20090224332Abstract: An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.Type: ApplicationFiled: February 9, 2009Publication date: September 10, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Tomohiko Tsutsumi, Toru Anezaki, Hideyuki Kojima, Taiji Ema
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Publication number: 20090215243Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.Type: ApplicationFiled: February 12, 2009Publication date: August 27, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Jusuke Ogura, Hikaru Kokura, Hideyuki Kojima, Toru Anezaki, Hiroyuki Ogawa, Junichi Ariyoshi
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Publication number: 20090154216Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: ApplicationFiled: February 6, 2009Publication date: June 18, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Patent number: 7539963Abstract: The semiconductor group comprises a first semiconductor device including a first design macro and a nonvolatile memory, and a second semiconductor device including a second design macro having identity with the first design macro and including no nonvolatile memory. The first design macro includes a first active region and a first device isolation region formed on a first semiconductor substrate. The second design macro includes a second active region and a second device isolation region formed on a second semiconductor substrate. A curvature radius of an upper end of the first active region in a cross section is larger than a curvature radius of an upper end of the second active region in a cross section. A difference in height between a surface of the first active region and a surface of the first device isolation region is larger than a difference in height between a surface of the second active region and a surface of the device isolation region.Type: GrantFiled: October 21, 2004Date of Patent: May 26, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki, Shinichi Nakagawa
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Patent number: 7521765Abstract: An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.Type: GrantFiled: December 27, 2004Date of Patent: April 21, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tomohiko Tsutsumi, Toru Anezaki, Hideyuki Kojima, Taiji Ema
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Patent number: 7511331Abstract: A semiconductor device is provided which has insulating film side wall spacers having a barrier function. The semiconductor device comprises: a gate oxide film and a gate electrode formed on and above a semiconductor substrate; source/drain regions formed in the semiconductor substrate; and first laminated side wall spacers having two or more layers and formed on side walls of the gate electrode, the first laminated side wall spacers including a nitride film as a layer other than an outermost layer, the outermost layer being made of an oxide film or an oxynitride film and having a bottom surface contacting the semiconductor substrate, the gate oxide film or a side wall spacer layer other than the nitride film.Type: GrantFiled: January 10, 2008Date of Patent: March 31, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Toru Anezaki
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Patent number: 7508692Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: GrantFiled: May 25, 2007Date of Patent: March 24, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Publication number: 20090045451Abstract: A method of manufacturing a semiconductor device that comprises the steps of: removing a second insulating film on a contact region of a first conductor; forming a second conductive film on the second insulating film; removing the second conductive film on the contact region of the first conductor to make the second conductive film into a second conductor; forming an interlayer insulating film (a third insulating film) covering the second conductor; forming a first hole in the interlayer insulating film on the contact region; and forming a conductive plug, which is electrically connected with the contact region, in the first hole.Type: ApplicationFiled: October 1, 2008Publication date: February 19, 2009Applicant: Fujitsu LimitedInventors: Taiji Ema, Toru Anezaki
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Publication number: 20090039411Abstract: According to an aspect of an embodiment, a semiconductor device has a substrate a first insulator formed in a first area of the substrate, and a second insulator formed in the second area of the substrate, a first transistor formed over a first device region surrounded by the first area, the first transistor having a first gate insulating film having a first thickness, the first gate insulating film being formed over the first device region, a first gate electrode formed over the first gate insulating film and the second transistor having a second gate insulating film formed over the second device region, a second gate insulating film having a second thickness less than the first thickness of the first gate insulating film, a second gate electrode formed over the second gate insulating film.Type: ApplicationFiled: August 7, 2008Publication date: February 12, 2009Applicant: FUJITSU LIMITEDInventor: Toru ANEZAKI
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Publication number: 20090001425Abstract: A method of manufacturing a semiconductor device has forming a first conductive film over a semiconductor substrate, etching the first conductive film, forming a plurality of first conductive patterns arranged in a first direction, and forming a side surface on an outside of a conductive pattern positioned at an end among the plurality of first conductive patterns such that the side surface has a first inclination angle smaller than a second inclination angle of a side surface on an inside of the conductive pattern positioned at the end, forming a first insulation film over the plurality of first conductive patterns, and forming a second conductive pattern over the first insulation film.Type: ApplicationFiled: June 27, 2008Publication date: January 1, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Junichi Ariyoshi, Toru Anezaki, Hiroshi Morioka
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Publication number: 20080299739Abstract: According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a first insulating film over a rear surface of a plurality of silicon substrates, annealing the plurality of silicon substrates to degas the oxide species in the first insulating film, and oxidizing the surface of the plurality of silicon substrates in a batch process after annealing the silicon substrates.Type: ApplicationFiled: May 9, 2008Publication date: December 4, 2008Applicant: FUJITSU LIMITEDInventors: Kazutaka YOSHIZAWA, Toru ANEZAKI, Katsuaki OOKOSHI, Teruki MORISHITA, Hajime WADA
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Publication number: 20080280406Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.Type: ApplicationFiled: July 15, 2008Publication date: November 13, 2008Applicant: FUJITSU LIMITEDInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Patent number: 7445989Abstract: A method of manufacturing a semiconductor device that comprises the steps of: removing a second insulating film on a contact region of a first conductor; forming a second conductive film on the second insulating film; removing the second conductive film on the contact region of the first conductor to make the second conductive film into a second conductor; forming an interlayer insulating film (a third insulating film) covering the second conductor; forming a first hole in the interlayer insulating film on the contact region; and forming a conductive plug, which is electrically connected with the contact region, in the first hole.Type: GrantFiled: January 28, 2005Date of Patent: November 4, 2008Assignee: Fujitsu LimitedInventors: Taiji Ema, Toru Anezaki
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Publication number: 20080237690Abstract: To provide a semiconductor device in which a high-performance and high-breakdown-voltage p-channel type MOS transistor having a surface channel structure and a memory cell are formed on the same substrate, and a method of manufacturing the semiconductor device. A method of manufacturing a semiconductor device including a stacked gate type nonvolatile memory cell and a p-channel type first transistor, includes: forming a gate insulating film of the first transistor on a semiconductor substrate; forming a tunnel insulating film of the stacked gate type nonvolatile memory cell on the semiconductor substrate; forming a first conductive layer containing an n-type impurity on the tunnel insulating film and the gate insulating film; and implanting p-type impurity ions to a region of the first conductive layer for forming the first transistor to turn the region of the first conductive layer into a p-type region.Type: ApplicationFiled: March 26, 2008Publication date: October 2, 2008Applicant: FUJITSU LIMITEDInventors: Toru ANEZAKI, Kenichi OKABE
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Patent number: 7414292Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.Type: GrantFiled: June 16, 2005Date of Patent: August 19, 2008Assignee: Fujitsu LimitedInventors: Taiji Ema, Hedeyuki Kojima, Toru Anezaki
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Publication number: 20080142871Abstract: A semiconductor device is provided which has insulating film side wall spacers having a barrier function. The semiconductor device comprises: a gate oxide film and a gate electrode formed on and above a semiconductor substrate; source/drain regions formed in the semiconductor substrate; and first laminated side wall spacers having two or more layers and formed on side walls of the gate electrode, the first laminated side wall spacers including a nitride film as a layer other than an outermost layer, the outermost layer being made of an oxide film or an oxynitride film and having a bottom surface contacting the semiconductor substrate, the gate oxide film or a side wall spacer layer other than the nitride film.Type: ApplicationFiled: January 10, 2008Publication date: June 19, 2008Applicant: FUJITSU LIMITEDInventor: Toru Anezaki
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Publication number: 20080090364Abstract: Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.Type: ApplicationFiled: December 7, 2007Publication date: April 17, 2008Applicant: FUJITSU LIMITEDInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Publication number: 20080067599Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.Type: ApplicationFiled: November 21, 2007Publication date: March 20, 2008Applicant: FUJITSU LIMITEDInventors: Tomohiko TSUTSUMI, Taiji EMA, Hideyuki KOJIMA, Toru ANEZAKI
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Patent number: 7323754Abstract: Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.Type: GrantFiled: June 29, 2005Date of Patent: January 29, 2008Assignee: Fujitsu LimitedInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki