Patents by Inventor Toru Azuma

Toru Azuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240166198
    Abstract: This behavior planning device includes: an emergency stop requesting unit which detects abnormality on the basis of obstacle information acquired from an obstacle information acquisition unit and a roadside information acquisition unit and outputs an emergency stop request; a stop position determination unit which calculates a stop position of an own vehicle on the basis of the emergency stop request and determines whether or not the stop position is in an area where advancement of another traffic participant is obstructed; and a behavior plan generation unit which, in a case where it is determined that the own vehicle will stop in the area where advancement of another traffic participant is obstructed, such as an intersection, generates a behavior plan for causing the own vehicle to stop outside the area or after passing over the area.
    Type: Application
    Filed: October 11, 2023
    Publication date: May 23, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroshi YAMADA, Toru Higuchi, Michitoshi Azuma, Kohei Mori, Takayuki Tanaka, Nariaki Takehara
  • Patent number: 11987408
    Abstract: A component mounting system including: a component mounting device group in which a plurality of component mounting devices that mount components supplied to a board transported in from an upstream side by a tape feeder and transport out the board to a downstream side, and cut a carrier tape after supplying the components by a cutter device and discharge scraps of carrier tape, are installed on a floor surface while being arranged in a direction of conveying the board; a main conveyor that is installed along an arrangement direction of the plurality of component mounting devices in a region on the floor surface under the component mounting device group, and transports the scraps of carrier tape discharged from each of the plurality of component mounting devices; and a scraps storage that is installed outside the region and stores the scraps of carrier tape transported by the main conveyor.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: May 21, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroki Kobayashi, Naoki Azuma, Chikara Takata, Yuzo Asano, Toru Chikuma, Hiroshi Satoh
  • Publication number: 20240157975
    Abstract: An autonomous driving integrated control system includes multiple roadside monitoring devices and an autonomous driving device, wherein the multiple roadside monitoring devices each have a sensor and a transmitter that transmits information of a detected object, and wherein the autonomous driving device has: a receiver unit; a vehicle abnormal state detection unit; an escape route generation unit that generates, per each of the roadside monitoring devices, intersection escape routes for escaping from the intersection; a selection unit that compares the thus-generated intersection escape routes with each other in terms of their collision-avoidance levels, to thereby make selections; a travelable distance calculation unit that calculates an abnormal-time travelable distance; a vehicle control unit that, when an abnormal state of the vehicle is detected, causes the vehicle to travel along a high-level intersection escape route corresponding to the abnormal-time travelable distance; and a vehicle operation unit.
    Type: Application
    Filed: August 28, 2023
    Publication date: May 16, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Michitoshi AZUMA, Kohei MORI, Toru HIGUCHI, Hiroshi YAMADA
  • Patent number: 7522823
    Abstract: In a thermal processing unit, a substrate is held by a local transport hand to be transported between a transfer section and a heating unit, and subjected to a heat processing by the heating unit. Also, the local transport hand is cooled by a cooling plate in the transfer section.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: April 21, 2009
    Assignee: Sokudo Co., Ltd.
    Inventors: Yasuhiro Fukumoto, Mitsuhiro Masuda, Toru Azuma
  • Patent number: 6937917
    Abstract: Provided is a substrate processing apparatus that can reduce power consumption, while maintaining throughput. In addition to a normal mode in which all units are activated, the apparatus is provided with an energy saving mode that is selectable. When the energy saving mode is selected, only essential units that are requisites for a substrate processing are activated and used in the substrate processing. If it is necessary to increase process efficiency, any additional unit may be activated and used in the processing. During standby, only an essential unit can be activated and the rest is halted, or alternatively, all units may be halted. The transition to the energy saving mode can occur when the standby state continues for a predetermined period of time after the normal mode is selected.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: August 30, 2005
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Kazuya Akiyama, Toru Azuma, Yasufumi Koyama
  • Publication number: 20050058440
    Abstract: In a thermal processing unit according to the present invention, a substrate is held by a local transport hand to be transported between a transfer section and a heating unit, and subjected to a heat processing by the heating unit. Also, the local transport hand is cooled by a cooling plate in the transfer section.
    Type: Application
    Filed: August 26, 2004
    Publication date: March 17, 2005
    Inventors: Yasuhiro Fukumoto, Mitsuhiro Masuda, Toru Azuma
  • Publication number: 20040122545
    Abstract: Provided is a substrate processing apparatus that can reduce power consumption, while maintaining throughput. In addition to a normal mode in which all units are activated, the apparatus is provided with an energy saving mode that is selectable. When the energy saving mode is selected, only essential units that are requisites for a substrate processing are activated and used in the substrate processing. If it is necessary to increase process efficiency, any additional unit may be activated and used in the processing. During standby, only an essential unit can be activated and the rest is halted, or alternatively, all units may be halted. The transition to the energy saving mode can occur when the standby state continues for a predetermined period of time after the normal mode is selected.
    Type: Application
    Filed: December 2, 2003
    Publication date: June 24, 2004
    Applicant: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Kazuya Akiyama, Toru Azuma, Yasufumi Koyama
  • Patent number: 4589139
    Abstract: An apparatus for inspecting a pattern consisting of light and dark areas formed on a planar test specimen according to design information, comprising: an imaging device for viewing the pattern to generate image information; a detector for generating a first signal upon detection that, in response to the image information, a boundary line between the light and dark areas of the pattern is bent in a determined stepping form in the direction of the plane; a memory for generating and storing a second signal, upon detection that the boundary line of the pattern has a bend of stepping form according to the design information, corresponding to the position in the imaging area of the bend in the design information; and an inspecting device for discriminating, upon generation of the first signal, the presence or absence of the second signal in the memory corresponding to the position of the first signal in the image area.
    Type: Grant
    Filed: January 31, 1983
    Date of Patent: May 13, 1986
    Assignee: Nippon Kogaku K. K.
    Inventors: Kazunari Hada, Norio Fujii, Toru Azuma, Kaoru Kikuchi, Junji Hazama
  • Patent number: 4506382
    Abstract: Two-dimensional pattern detecting apparatus provided with register for serially receiving binary signals obtained from analog signals of a two-dimensional pattern and adapted to divide the pattern into pixels and to represent the density of bright and dark for pixels by the binary signals. The apparatus further includes a processing circuit adapted to compare with predetermined patterns a pattern composed of 8 peripheral pixels of a partial area of 3.times.3 pixels within the two-dimensional pattern, on the basis of the binary signals stored in the register. The processing circuit outputs a binary signal of a logic value stored in said register corresponding to a central pixel of the partial area when the pattern of the 8 pixels coincides with one of said predetermined patterns, and to outputs a binary signal of a logic value prevailing in 8 binary signals stored in the register corresponding to the 8 pixels when the pattern of the 8 pixels does not coincide with any of the predetermined patterns.
    Type: Grant
    Filed: April 21, 1982
    Date of Patent: March 19, 1985
    Assignee: Nippon Kogaku K.K.
    Inventors: Kazunari Hada, Norio Fujii, Atsushi Kawahara, Toru Azuma, Junji Hazama
  • Patent number: 4479145
    Abstract: A pattern examining in which a pattern on an examined object such as reticle or mask is scanned to produce image binary signals of picture elements; binary information corresponding to a local area on the examined object is serially extracted from the image binary signals; and shape detection is effected for detecting by means of the binary information whether or not the pattern in the local area possesses a determined geometric shape or characteristics. The result of the shape detection is compared with the information on design relating to the geometric shape or characteristics which the pattern on the examined object should possess.
    Type: Grant
    Filed: July 22, 1982
    Date of Patent: October 23, 1984
    Assignee: Nippon Kogaku K.K.
    Inventors: Toru Azuma, Junji Hazama, Atsushi Kawahara, Kazunari Hada, Norio Fujii
  • Patent number: 4472738
    Abstract: A pattern defect testing apparatus comprises a first detection circuit which defines a first detection area on a two-dimensional pattern and produces a first detection signal when all digital signals representative of densities of picture cells in the first detection area have the same logical value, a second detection circuit which defines a second detection area on the two-dimensional pattern and produces a second detection signal when at least one of digital signals representative of densities of picture cells in the second detection area has a logical value different from that of the digital signals to the first detection circuit, and a discriminating circuit for discriminating the presence of a defect in the second detection area when the first and second detection signals are produced.
    Type: Grant
    Filed: May 24, 1982
    Date of Patent: September 18, 1984
    Assignee: Nippon Kogaku K.K.
    Inventors: Kazunari Hada, Norio Fujii, Atsushi Kawahara, Toru Azuma, Junji Hazama
  • Patent number: D968397
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 1, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Toru Azuma, Taichiro Ishii