Abstract: In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chippthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing.The digital signal processing unit is made a calculation unit that handles fixed-point data, and an instruction calling for execution of a fixed-point data calculation is provided separately from the conventional integer calculation instruction.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: A digital signal processor that includes an execution unit, a condition code register, a program memory, a program control unit, and an instruction decoder. The program memory stores a sequence of instruction words and includes an instruction word that has at least one field that identifies a data processing operation to be performed by the execution unit. The instruction word also includes a condition code field that identifies a predefined condition and also identifies whether said condition code register should be updated when the data processing operation is performed by the execution unit. The program control unit outputs an instruction address to the program memory so as to select the instruction word in the program memory. The instruction decoder decodes the selected instruction word. It includes decoder circuitry for decoding the at least one field to generate control signals for controlling the execution unit to perform the specific data processing operation.

Abstract: A digital signal processor (DSP) provides an improvement in the interfacing and sharing of external memory devices. Specifically, the digital signal processor is provided with a parallel interface for communicating with external memory devices, a chip select decoder located on-chip for selectably enabling external memory devices, and a wait status controller for holding processor operation until the selected memory device is ready. The memory architecture is configurable for internal or external wait state generation and memory sharing with other DSPs so that a plurality of varying speed memory devices may be accessed. The chip select decoder includes a programmable register for storing a mode configuration word for defining a plurality of external memory configurations.

Abstract: A digital signal processor that includes an instruction memory, a program control unit, and an instruction decoder. The instruction memory stores a sequence of instruction words including DSP instruction words and RISC instruction words. The program control unit outputs an instruction address to the instruction memory so as to select one instruction word in the instruction memory. Every DSP instruction word identifies one data processing operation and one data transfer operation to be performed. The DSP instruction words include a predefined DSP instruction word having separate source and destination fields for specifying register locations for data sources and data destinations. The RISC instruction words include a predefined RISC instruction word corresponding to the predefined DSP instruction word. The predefined RISC instruction word has separate source and destination fields for specifying register locations for data sources and data destinations.

Abstract: A single chip digital signal processor (DSP) includes memory mapped resources and an on-chip direct memory access controller (DMAC). The memory mapped resources of the DSP include an on-chip program memory, an on-chip data memory, internal registers and memory mapped external memories and peripheral devices. The DMAC includes a host computer interface that processes host originated data transfer commands for transferring data to and from memory mapped resources of the DSP, and commands for setting the mode of operation of the DSP. The DMAC also has a dedicated interrupt controller for handling interrupts from a host computer and from peripheral devices. The DMAC processes interrupts from the host while a primary direct memory access transfer is being performed by the DMAC without having to store address register and count register information in a memory stacking area.

Abstract: A single chip digital signal processor (DSP) includes memory mapped resources and an on-chip direct memory access controller (DMAC). The memory mapped resources of the DSP include an on-chip program memory, an on-chip data memory, internal registers and memory mapped external memories and peripheral devices. The DMAC includes separate address and count registers for handling a primary data transfer and two interrupt data transfers. The count registers share the same decrementer and the address registers share the same address computation circuit. The DMAC also has a dedicated interrupt controller for handling interrupts from a host computer and from peripheral devices. The DMAC processes interrupts from the host and two peripheral devices while a primary direct memory access transfer is being performed by the DMAC without having to store address register and count register information in a memory stacking area.

Abstract: There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks respectively provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

Abstract: A data processor comprises a plurality of registers 1 (registers a to d), a plurality of data saving stack memory devices 2 coupled to the registers 1 for exclusive use thereof, respectively, and an instruction decoder for decoding instructions for controlling the registers 1 and the data saving stack memory devices 2 in accordance with the result of the instruction decoding. In response to an instruction "PUSH", the contents of the registers 1 (registers a to d) are selectively saved to the data saving stack memory device 2. In response to a instruction "POP", the contents of the data saving stack memory devices 2 are selectively restored to the registers 1 (registers a to d). Each of the instructions "PUSH" and "POP" has a field for indicating need or needlessness of the saving and restoration for each of the registers 1 and each of the data saving memories 2.

Abstract: There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks are provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

Abstract: An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memory, combines the two sequentially adjacent instructions into a single long instruction word when the two instructions meet predefined criteria for being combined. The first of the two instructions is combined with a no-operation instruction to generate a long instruction word when the predefined criteria are not met. In that case, the second instruction [may be accessed again] is used during the next instruction fetch cycle as the first of the two sequentially adjacent instructions to be processed during that next instruction fetch cycle.

Abstract: A neural net signal processor provided with a single layer neural net constituted of N neuron circuits which sums the results of the multiplication of each of N input signals Xj(j=1 to N) by a coefficient mij to produce a multiply-accumulate value ##EQU1## thereof, in which input signals Xj(j=1 to N) for input to the single layer neural net are input as serial input data, comprising: a multiplicity of systolic processor elements SPE-1(i=1 to M), each comprised of a two-state input data delay latch; a coefficient memory; means for multiplying and summing for multiply-accumulate output operations; an accumulator; a multiplexor for selecting a preceding stage multiply-accumulate output Sk(k=1 to i-1) and the multiply-accumulate product Si computed by the said circuit; wherein the multiplicity of systolic processor elements are serially connected to form an element array and element multiply-accumulate output operations are executed sequentially to obtain the serial multiply-accumulate outputs Si(i=1 to M) of one

Abstract: A multimedia bidirectional broadcast system including a broadcast station and subscriber terminals. The broadcast station includes a main control unit having therein a data base control table in which program and commerical down load sequences are recorded depending on a setting effected by a subscriber, a motion picture program data base, a commerical data base, a program transmitter for effecting accesses and transmissions of transmission programs onto transmission lines based on the setting of the main control unit, a commercial transmitter for accessing the commerical data base and for transmitting content thereof based on the setting of the main control unit, an image encoder for achieving a bandwidth compression on a video signal, a cell assembler for processing data to be transmitted onto a broadband transmission line so as to generate a cell of the data, and an asynchronous transfer mode exchange for delivering the cell to a subscriber system associated therewith.

Abstract: A digital signal processor for computing a vector product between a column vector input signal including a plurality of data items (x0, x1, x2, . . . , x7) and a matrix including a predetermined number of coefficient data items so as to produce a column vector output signal including a plurality of data items (y0, y1, y2, . . . , y7). In a first cycle, the leading data x0 of the column vector input signal is stored in a first store unit (Rin), whereas during this period of time, in a second cycle shorter in time than the first cycle, the data items (c0, c1, c2, . . . , c7) in the row direction constituting a first portion of the matrix are sequentially read out such that both data items are multiplied, thereby storing the multiplication results in an accumulator. A similar data processing is repeatedly executed so as to obtain, based on the outputs from the accumulator, a column vector output signal constituted by the plurality of data items (y0, y1, y2, . . . , y7).

Abstract: According to the present invention, the number of elements of a signal processing circuit or the like can be drastically reduced by conducting a time-multiplex processing. In a transversal filter having a coefficient of symmetry of 16 taps, for example, the prior art requires about 58,000 transistors. In case four signal processing cores (i.e., SPC) having a function of four taps are used, the number of transistors required can be reduced to about 34,000 by a duplexing process. In case two SPCs having a function of eight taps are used, the number can be reduced to about 19,000 by a quadplexing process. In case, moreover, one SPC having a function of sixteen taps is used, the number can be reduced to about 13,000 by an octaplexing process. Here, the reason why the number of elements is not halved even if the number of the SPCs is halved is that the number of elements to be used in control circuits, memories and so on increases.

Abstract: In a thin film device having a hydrogenated amorphous silicon film, a metal layer is formed on the hydrogenated amorphous silicon film and then the metal layer is removed. A resulting reaction layer formed on the hydrogenated amorphous silicon film is used as a resistor.

Abstract: A photosensor comprises a first conductive layer formed on a given substrate, a one-dimensional array of a plurality of unit picture elements formed on the first conductive layer to extend in the longitudinal direction thereof, each unit picture element having a photodiode and a blocking diode connected in series with the photodiode in a relationship of reversed rectifying direction therewith, a second conductive layer for connecting together, at one end, respective unit picture elements belonging to each of at least two unit picture element groups having each at least two of adjacent unit picture elements, and a third conductive layer for connecting together, at the other end, corresponding unit picture elements in the respective groups, the set of the photodiode and blocking diode in the respective groups being made of the same semiconductor material. Dispersion of outputs from the respective unit picture elements can be minimized.

Abstract: An optical image sensor apparatus in which a plurality of photosensors arrayed in a primary scanning direction are scanned to produce readout signals. The plurality of photosensors are classified into a number of groups each including a predetermined number of the photosensors, wherein those photosensors occupying equivalently the same position in the different groups are combined in common. The outputs of the photosensors are sequentially and selectively scanned on a group basis to produce readout signal for each of the groups. To provide a scanning readout operation at an increased speed, an integrating circuit is provided for each of the photosensors exchangeably for each group. The outputs of all the photosensors belonging to a given one of the group are simultaneously supplied to the respective integrating circuits. The readout signal output is obtained by scanning sequentially the outputs of the integrating circuits.

Abstract: In a photoelectric conversion element including at least a first electrode and a photoconductive layer having an amorphous material whose indispensable constituent is silicon and which contains hydrogen as an essential constituent element on a predetermined substrate, the present invention discloses a photoelectric conversion element wherein said layer of the amorphous material is disposed on said first electrode via a light transmitting or light semi-transmitting metallic layer for adhesion with respect to said amorphous material. As said metallic layer for adhesion, preferred is a layer consisting of at least one metal selected from the group consisting of Ta, Cr, W, Nd, Mo, V and Ti. Thus, adhesion between said substrate and said amorphous material can be improved.

Abstract: The present invention consists in providing a CCD type color solid-state imager in which color signals respectively separated in time can be derived from picture elements for respective colors arrayed in the shape of a matrix and which permits interlacing without degrading a resolution and without causing image lag. Concretely, pairs of CCD shift registers which are electrically insulated and separated and which run in the vertical direction are arrayed in the horizontal direction, signal charges stored in adjacent picture elements are sent into the individual opposing CCD registers through transfer gates arrayed in a checkerboard pattern, and signal charges transferred in time sequence are distributed to a plurality of CCD shift registers which run in the horizontal direction, whereby a CCD type color solid-state imager having a high resolution and exhibiting no image lag is obtained.