Patents by Inventor Toru Koga
Toru Koga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8871245Abstract: A transdermal patch for the treatment of Alzheimer's disease includes: a backing, a rivastigmine-containing layer, a pressure-sensitive adhesive layer, and a release liner. In the transdermal patch, the rivastigmine-containing layer contains rivastigmine and an alkyl (meth)acrylate resin, the pressure-sensitive adhesive layer is composed of an acrylic pressure-sensitive adhesive containing a (meth)acrylic acid ester having a hydroxy group, and neither the rivastigmine-containing layer nor the pressure-sensitive adhesive layer contains an anti-oxidizing agent.Type: GrantFiled: February 28, 2012Date of Patent: October 28, 2014Assignee: Nichiban Co., Ltd.Inventors: Takao Hiraoka, Shuta Nakanami, Toru Koga
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Publication number: 20130220846Abstract: A transdermal patch for the treatment of Alzheimer's disease includes: a backing, a rivastigmine-containing layer, a pressure-sensitive adhesive layer, and a release liner. In the transdermal patch, the rivastigmine-containing layer contains rivastigmine and an alkyl (meth)acrylate resin, the pressure-sensitive adhesive layer is composed of an acrylic pressure-sensitive adhesive containing a (meth)acrylic acid ester having a hydroxy group, and neither the rivastigmine-containing layer nor the pressure-sensitive adhesive layer contains an anti-oxidizing agent.Type: ApplicationFiled: February 28, 2012Publication date: August 29, 2013Applicant: NICHIBAN CO., LTD.Inventors: Takao Hiraoka, Shuta Nakanami, Toru Koga
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Publication number: 20100321983Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.Type: ApplicationFiled: March 5, 2010Publication date: December 23, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Publication number: 20100220540Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.Type: ApplicationFiled: March 5, 2010Publication date: September 2, 2010Applicant: FUJISU MICROELECTRONICS LIMITEDInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Patent number: 7706209Abstract: A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.Type: GrantFiled: December 22, 2005Date of Patent: April 27, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Patent number: 7558660Abstract: When a line pressure PL serving as a source pressure of a primary pulley (2) and a secondary pulley (3) is controlled on the basis of a control deviation ?Step, which is the deviation between a step count StepMdl of a step motor (27) corresponding to a target speed ratio I (o) and a value obtained by adding a target deviation GTstep and a starting learned value Gstep to a step count Bstep of the step motor (27) corresponding to an actual speed ratio ip, the engine torque varies dramatically beyond the range of a predetermined value T1 and a predetermined value T2 during a predetermined time period t1, a learning error determination relating to the starting learned value Gstep is prohibited for a predetermined time period t2.Type: GrantFiled: October 2, 2006Date of Patent: July 7, 2009Assignee: Jatco LtdInventors: Tetsuya Izumi, Hironori Nihei, Seonjae Kim, Takeshi Chibahara, Toru Koga
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Publication number: 20070082771Abstract: When a line pressure PL serving as a source pressure of a primary pulley (2) and a secondary pulley (3) is controlled on the basis of a control deviation ?Step, which is the deviation between a step count StepMdl of a step motor (27) corresponding to a target speed ratio I (o) and a value obtained by adding a target deviation GTstep and a starting learned value Gstep to a step count Bstep of the step motor (27) corresponding to an actual speed ratio ip, the engine torque varies dramatically beyond the range of a predetermined value T1 and a predetermined value T2 during a predetermined time period t1, a learning error determination relating to the starting learned value Gstep is prohibited for a predetermined time period t2.Type: ApplicationFiled: October 2, 2006Publication date: April 12, 2007Inventors: Tetsuya Izumi, Hironori Nihei, Seonjae Kim, Takeshi Chibahara, Toru Koga
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Patent number: 7079443Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.Type: GrantFiled: August 1, 2003Date of Patent: July 18, 2006Assignee: Fujitsu LimitedInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Publication number: 20060098523Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.Type: ApplicationFiled: December 22, 2005Publication date: May 11, 2006Inventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Patent number: 7032142Abstract: A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.Type: GrantFiled: October 17, 2002Date of Patent: April 18, 2006Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Waichiro Fujieda, Kota Hara, Toru Koga, Katsuhiro Mori
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Patent number: 6845055Abstract: A semiconductor memory that can make the transition from a power-down state in a synchronous mode to an asynchronous mode without setting by a control register and that needs no extra circuits. A state selection section chooses, by selecting an existing internal signal the level of which changes in the power-down state or an existing internal signal the level of which does not change in the power-down state in accordance with a state selection signal inputted in advance and passing a signal selected to a synchronous/asynchronous mode setting section, whether the semiconductor memory should make the transition from the power-down state to a standby state in the synchronous mode or a standby state in the asynchronous mode. In accordance with the selection by the state selection section, the synchronous/asynchronous mode setting section generates a signal for causing the semiconductor memory to make the transition between the synchronous mode and the asynchronous mode.Type: GrantFiled: June 15, 2004Date of Patent: January 18, 2005Assignee: Fujitsu LimitedInventors: Toru Koga, Tomohiro Kawakubo, Tatsuya Kanda
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Patent number: 6831870Abstract: Main memory units are each composed of an even number of sub memory units having different addresses. The sub memory units have memory cells, bit lines corresponding to different data terminals with numbers, sense amplifiers, and column switch circuits for connecting the bit lines to data bus lines. Column switch areas of the main memory units are formed in mirror symmetry. Consequently, the sequence of the data terminal numbers of the bit lines in the case of relief where a redundancy memory unit is used can be easily made the same as in the case of non-relief where the redundancy memory unit is not used. As a result, at the time of defect analysis, the sequence of the bit lines need not be taken into account regardless of whether the product is a relief product or non-relief product. This allows a reduction in the time necessary for defect analysis.Type: GrantFiled: July 29, 2003Date of Patent: December 14, 2004Assignee: Fujitsu LimitedInventor: Toru Koga
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Publication number: 20040114442Abstract: Main memory units are each composed of an even number of sub memory units having different addresses. The sub memory units have memory cells, bit lines corresponding to different data terminals with numbers, sense amplifiers, and column switch circuits for connecting the bit lines to data bus lines. Column switch areas of the main memory units are formed in mirror symmetry. Consequently, the sequence of the data terminal numbers of the bit lines in the case of relief where a redundancy memory unit is used can be easily made the same as in the case of non-relief where the redundancy memory unit is not used. As a result, at the time of defect analysis, the sequence of the bit lines need not be taken into account regardless of whether the product is a relief product or non-relief product. This allows a reduction in the time necessary for defect analysis.Type: ApplicationFiled: July 29, 2003Publication date: June 17, 2004Applicant: FUJITSU LIMITEDInventor: Toru Koga
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Publication number: 20040022091Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.Type: ApplicationFiled: August 1, 2003Publication date: February 5, 2004Applicant: FUJITSU LIMITEDInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Patent number: 6683491Abstract: First and second voltage generators generate a first internal power supply voltage to be supplied to a first internal power supply line and a second internal power supply voltage to be supplied to a second internal power supply line, respectively. A short circuit shorts the first and second internal power supply lines when operations of both the first and second voltage generators are suspended. The first and second internal power supply lines become floating, and charges stored in the respective internal power supply lines drain out gradually. Here, since the charges are redistributed to both of the internal power supply lines, the first and second internal power supply voltages become equal in value as they drop off. Consequently, the first and second internal power supply voltages can be prevented from inversion, and internal circuits connected to both the first and second internal power supply lines can be precluded from malfunctioning.Type: GrantFiled: March 27, 2002Date of Patent: January 27, 2004Assignee: Fujitsu LimitedInventors: Toru Koga, Shinya Fujioka, Katsuhiro Mori
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Patent number: 6628564Abstract: A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.Type: GrantFiled: June 25, 1999Date of Patent: September 30, 2003Assignee: Fujitsu LimitedInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Patent number: 6605963Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.Type: GrantFiled: October 5, 1999Date of Patent: August 12, 2003Assignee: Fujitsu LimitedInventors: Ayako Kitamoto, Masato Matsumiya, Satoshi Eto, Masato Takita, Toshikazu Nakamura, Hideki Kanou, Kuninori Kawabata, Masatomo Hasegawa, Toru Koga, Yuki Ishii
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Publication number: 20030106010Abstract: A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.Type: ApplicationFiled: October 17, 2002Publication date: June 5, 2003Applicant: FUJITSU LIMITEDInventors: Shinya Fujioka, Waichiro Fujieda, Kota Hara, Toru Koga, Katsuhiro Mori
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Patent number: D700129Type: GrantFiled: September 14, 2011Date of Patent: February 25, 2014Assignee: Nifco Inc.Inventor: Toru Koga
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Patent number: D700695Type: GrantFiled: April 5, 2011Date of Patent: March 4, 2014Assignee: Nifco Inc.Inventor: Toru Koga