Patents by Inventor Toru Miwa

Toru Miwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10978156
    Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 13, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Aaron Lee, Gerrit Jan Hemink, Ken Oowada, Toru Miwa
  • Patent number: 10885984
    Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Patent number: 10854619
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: December 1, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Patent number: 10734080
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: August 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Publication number: 20200185397
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Publication number: 20200185039
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Patent number: 10635526
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Yibo Yin, Henry Zhang, Po-Shen Lai, Vijay Chinchole, Spyridon Georgakis, Yan Li, Hiroyuki Mizukoshi, Toru Miwa, Jayesh Pakhale, Tz-Yi Liu
  • Publication number: 20200005871
    Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang YANG, Aaron LEE, Gerrit Jan HEMINK, Ken OOWADA, Toru MIWA
  • Publication number: 20180357123
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.
    Type: Application
    Filed: March 23, 2018
    Publication date: December 13, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Yibo Yin, Henry Zhang, Po-Shen Lai, Vijay Chinchole, Spyridon Georgakis, Yan Li, Hiroyuki Mizukoshi, Toru Miwa, Jayesh Pakhale, Tz-Yi Liu
  • Patent number: 9941297
    Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 10, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Kota Funayama, Toru Miwa, Hiroyuki Ogawa
  • Publication number: 20170263642
    Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
    Type: Application
    Filed: May 30, 2017
    Publication date: September 14, 2017
    Applicant: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Kota Funayama, Toru Miwa, Hiroyuki Ogawa
  • Patent number: 9691781
    Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 27, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Kota Funayama, Toru Miwa, Hiroyuki Ogawa
  • Publication number: 20170162592
    Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 8, 2017
    Applicant: SanDisk Technologies Inc.
    Inventors: Masatoshi Nishikawa, Kota Funayama, Toru Miwa, Hiroyuki Ogawa
  • Patent number: 9646981
    Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 9, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Ryoichi Honma, Toru Miwa, Masahide Matsumoto, Yuki Mizutani, Hiroaki Koketsu
  • Patent number: 9595535
    Abstract: Word line switches in a word line decoder circuitry for a three-dimensional memory device can be formed as vertical field effect transistors overlying contact via structures to the electrically conductive layers for word lines. Via cavities in a dielectric material portion overlying stepped surfaces of the electrically conductive layers can be filled with a conductive material and recessed to form contact via structures. After forming lower active regions in the recesses, gate electrodes can be formed and patterned to form openings in areas overlying the contact via structures. Gate dielectrics can be formed on the sidewalls of the openings, and transistor channels can be formed inside the openings of the gate electrodes. Upper active regions can be formed over the transistor channels.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: March 14, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Makoto Yoshida, Kazutaka Yoshizawa, Takuya Ariki, Toru Miwa
  • Patent number: 9589981
    Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: March 7, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Ryoichi Honma, Toru Miwa, Hiroaki Koketsu, Johann Alsmeier
  • Publication number: 20160365352
    Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Inventors: Masatoshi NISHIKAWA, Ryoichi HONMA, Toru MIWA, Hiroaki KOKETSU, Johann ALSMEIER
  • Publication number: 20160365351
    Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Inventors: Masatoshi NISHIKAWA, Ryoichi HONMA, Toru MIWA, Masahide MATSUMOTO, Yuki MIZUTANI, Hiroaki KOKETSU
  • Patent number: RE46014
    Abstract: Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to determine which storage elements have a threshold voltage below a reference voltage level associated with the tracked state. By tracking which storage elements are in the tracked state, elements associated with other states may be filtered out such that an accurate assessment may be made as to which storage elements were under-programmed. From this information, a determination may be made whether the word line is defective. For example, if too many storage elements are under-programmed, this may indicate a broken word line.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: May 24, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Manabu Sakai, Toru Miwa
  • Patent number: RE46264
    Abstract: When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: January 3, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Gerrit Jan Hemink, Shih-Chung Lee, Toru Miwa, Yupin Fong, Jun Wan, Ken Oowada