Abstract: An encoding device converts four-channel or five-channel audio signals to two-channel audio signals, which are then subjected to compression in accordance with the MPEG standard. Matrix coefficients are calculated based on the two-channel audio signals. A decoding device receives the compressed two-channel audio signals together with the matrix coefficient. The compressed two-channel audio signals are expanded and are then subjected to prescribed arithmetic operations using the matrix coefficients. Thus, the decoding device reproduces the original audio signals. The decoding device, which is normally actualized by a digital signal processor (DSP), is noticeably reduced in amounts of calculations and is simplified in circuit configuration because of the elimination of calculations of matrix coefficients therein.

Abstract: A digital signal processing circuit, which is embodied by a digital signal processor (i.e., DSP), comprises at least an address counter and a coefficient RAM which is provided to store coefficients used for convolution processing to be performed. An overall storage area of the coefficient RAM exists between a first address and a last address. An external device provides control information including an initial count number and up/down information. The address counter counts a number of pulses included in a timing signal, which is produced in synchronism with bit clocks in a sampling period, so as to output a count number as a write address for the coefficient RAM. The address counter performs either an up-counting or a down-counting in accordance with the up/down information; and the count number thereof is increased or decreased from the initial count number. Hence, the coefficients sequentially inputted are written into the coefficient RAM at the respective write addresses.

Abstract: A digital signal processing circuit, which is configured by a digital signal processor (i.e., DSP), includes at least a data memory, a coefficient memory, a calculation portion and an interpolation portion. The data memory stores a plurality of digital data which are sequentially supplied thereto, while the coefficient memory stores a plurality of coefficients in connection with the plurality of digital data. The calculation portion performs a specific calculation (e.g., multiplication), using the coefficient, on the digital data. When a new coefficient is given with respect to one of the coefficients designated, the interpolation portion performs interpolation processing on the designated coefficient so as to successively shift it to the new coefficient. The coefficient successively shifted is stored in the coefficient memory. Hence, the calculation portion performs the calculation, using the coefficient successively shifted, on the digital data.