Patents by Inventor Toru Takeshita
Toru Takeshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11969857Abstract: A method of producing a glass article includes holding a carrier having a circular shape, in which a glass substrate having a circular shape is retained, with an upper surface plate and a lower surface plate; and polishing the glass substrate by rotating the carrier with respect to the upper surface plate and the lower surface plate, to obtain the glass article. The glass substrate is disposed in the carrier such that, in a top plan view, a center of the carrier is included in a region of the glass substrate, and a center of the glass substrate is shifted from the center of the carrier.Type: GrantFiled: October 19, 2022Date of Patent: April 30, 2024Assignee: AGC INC.Inventors: Toru Momose, Osamu Sato, Hirofumi Yamamoto, Nobuhiko Takeshita
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Patent number: 11621693Abstract: An acoustic wave device includes an element substrate having piezoelectricity, an interdigital transducer electrode provided on the element substrate, and a mold resin covering the element substrate. When viewed in a cross section, the element substrate includes an interdigital transducer formation region in which the interdigital transducer electrode is provided and a pair of interdigital transducer non-formation regions in which the interdigital transducer electrode is not provided and located on both sides of the interdigital transducer formation region, and a thickness dimension of a center portion, in a width direction, of the interdigital transducer formation region is less than at least one of thickness dimensions of center portions, in the width direction, of the interdigital transducer non-formation regions.Type: GrantFiled: June 6, 2019Date of Patent: April 4, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Toru Takeshita
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Patent number: 11581868Abstract: An acoustic wave device includes an acoustic wave substrate including a first main surface and a second main surface, IDT electrodes provided on the first main surface, and sealing resin covering at least the second main surface of the acoustic wave substrate. A hollow is provided in a region where the IDT electrodes on the first main surface of the acoustic wave substrate is located. The sealing resin has through-holes each extending from a top surface 13B of the sealing resin to the second main surface of the acoustic wave substrate. The acoustic wave substrate is made of silicon or includes a layer made of silicon.Type: GrantFiled: April 1, 2020Date of Patent: February 14, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Toru Takeshita
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Publication number: 20220158614Abstract: An acoustic wave device includes a piezoelectric substrate including a first side defining a portion of an outer circumference, and a second side shorter than the first side, IDT electrodes on the piezoelectric substrate, a support including a cavity and on the piezoelectric substrate to surround the IDT electrodes with the cavity, first and second partitioning supports on the piezoelectric substrate and disposed in an inner side of the cavity of the support, and a cover on the support and covering the cavity of the support. An extending direction of the first partitioning support is parallel or substantially parallel to an extending direction of the first side of the piezoelectric substrate. An extending direction of the second partitioning support is orthogonal or substantially orthogonal to the extending direction of the first partitioning support.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Tomoaki TEZUKA, Toru TAKESHITA, Shinichi FUKUDA
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Patent number: 11005445Abstract: An electronic component including a pad electrode provided on a wiring electrode and a Au bump provided on the pad electrode, wherein the uppermost layer of the wiring electrode is a first Ti layer, the uppermost layer of the pad electrode is a Au layer, and the thickness of the first Ti layer in at least a portion on which the Au bump is superposed in plan view is greater than the thickness of at least a portion of the first Ti layer in a portion on which the Au bump is not superposed in plan view.Type: GrantFiled: December 12, 2019Date of Patent: May 11, 2021Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Ryuta Yamada, Yasuyuki Toyota, Masaharu Fujiya, Toru Takeshita, Masaaki Shimada
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Patent number: 10812042Abstract: In an electronic component, electrodes defining functional portions are provided on a piezoelectric substrate. In order to define a hollow portion which the functional portions face, there are provided a first support with a frame shape, and second supports on the piezoelectric substrate in an inner side region surrounded by the first support. A cover is laminated on the first support as well as on the second supports to define the hollow portion. A height of each of the second supports is higher than a height of the first support.Type: GrantFiled: August 10, 2017Date of Patent: October 20, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Toru Takeshita
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Patent number: 10756698Abstract: An elastic wave device includes a multilayer film including a piezoelectric thin film laminated on a support substrate. In a region outside a region in which an IDT electrode is provided, the multilayer film is not disposed. A first insulating layer extends from at least a portion of the region to a region on the piezoelectric thin film. A wiring electrode extends to a region on the first insulating layer from a region on the piezoelectric thin film and to extend to a region on a portion of the first insulating layer located in the region. A support layer including a cavity defining a hollow space is provided on the support substrate. The support layer includes, on the wiring electrode, a portion extending from the region to a region above an inner end of the first insulating layer.Type: GrantFiled: March 29, 2019Date of Patent: August 25, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Takashi Yamane, Tsutomu Takai, Toru Takeshita
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Publication number: 20200228090Abstract: An acoustic wave device includes an acoustic wave substrate including a first main surface and a second main surface, IDT electrodes provided on the first main surface, and sealing resin covering at least the second main surface of the acoustic wave substrate. A hollow is provided in a region where the IDT electrodes on the first main surface of the acoustic wave substrate is located. The sealing resin has through-holes each extending from a top surface 13B of the sealing resin to the second main surface of the acoustic wave substrate. The acoustic wave substrate is made of silicon or includes a layer made of silicon.Type: ApplicationFiled: April 1, 2020Publication date: July 16, 2020Inventor: Toru TAKESHITA
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Patent number: 10715102Abstract: A filter device includes a first filter chip including a first signal terminal and a second filter chip including a second signal terminal that are mounted above a package substrate including a substrate main body. First and second signal electrode pads are provided on a first main surface of the package substrate and are respectively joined to the first and second signal terminals. First and second outer terminals are provided on a second main surface of the substrate main body. The first and second signal electrode pads and the first and second outer terminals are connected to each other with first and second wirings, respectively. The second outer terminal is located at the first signal electrode pad side and the first outer terminal is located at the second signal electrode pad side when seen from above.Type: GrantFiled: June 7, 2018Date of Patent: July 14, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Toru Takeshita
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Publication number: 20200204152Abstract: An electronic component including a pad electrode provided on a wiring electrode and a Au bump provided on the pad electrode, wherein the uppermost layer of the wiring electrode is a first Ti layer, the uppermost layer of the pad electrode is a Au layer, and the thickness of the first Ti layer in at least a portion on which the Au bump is superposed in plan view is greater than the thickness of at least a portion of the first Ti layer in a portion on which the Au bump is not superposed in plan view.Type: ApplicationFiled: December 12, 2019Publication date: June 25, 2020Inventors: Ryuta YAMADA, Yasuyuki TOYOTA, Masaharu FUJIYA, Toru TAKESHITA, Masaaki SHIMADA
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Patent number: 10622965Abstract: A surface acoustic wave device assembly includes a collective board, first circuit portions provided on the collective board and respectively including first hot terminals and first ground terminals, a second circuit portion provided on the collective board and including second hot terminals and second ground terminals, and a power supply wiring provided on the collective board so as to surround the periphery of the first circuit portions and the second circuit portion. The first circuit portions include surface acoustic wave devices defining band pass filters. The second circuit portion defines a band pass filter. The first ground terminals and first hot terminals, and the second ground terminal are connected to the power supply wiring, the second hot terminals are not connected to the power supply wiring, and pass bands of the surface acoustic wave devices and a pass band of the band pass filter defined by the second circuit portion are the same or substantially the same.Type: GrantFiled: July 17, 2017Date of Patent: April 14, 2020Assignee: Murata Manufacturing Co., Ltd.Inventors: Toru Takeshita, Seiji Kai, Takashi Naka, Motoji Tsuda, Mitsuyoshi Hira
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Publication number: 20190305748Abstract: An elastic wave device includes a multilayer film including a piezoelectric thin film laminated on a support substrate. In a region outside a region in which an IDT electrode is provided, the multilayer film is not disposed. A first insulating layer extends from at least a portion of the region to a region on the piezoelectric thin film. A wiring electrode extends to a region on the first insulating layer from a region on the piezoelectric thin film and to extend to a region on a portion of the first insulating layer located in the region. A support layer including a cavity defining a hollow space is provided on the support substrate. The support layer includes, on the wiring electrode, a portion extending from the region to a region above an inner end of the first insulating layer.Type: ApplicationFiled: March 29, 2019Publication date: October 3, 2019Inventors: Takashi YAMANE, Tsutomu TAKAI, Toru TAKESHITA
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Publication number: 20190288666Abstract: An acoustic wave device includes an element substrate having piezoelectricity, an interdigital transducer electrode provided on the element substrate, and a mold resin covering the element substrate. When viewed in a cross section, the element substrate includes an interdigital transducer formation region in which the interdigital transducer electrode is provided and a pair of interdigital transducer non-formation regions in which the interdigital transducer electrode is not provided and located on both sides of the interdigital transducer formation region, and a thickness dimension of a center portion, in a width direction, of the interdigital transducer formation region is less than at least one of thickness dimensions of center portions, in the width direction, of the interdigital transducer non-formation regions.Type: ApplicationFiled: June 6, 2019Publication date: September 19, 2019Inventor: Toru TAKESHITA
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Publication number: 20180287588Abstract: A filter device includes a first filter chip including a first signal terminal and a second filter chip including a second signal terminal that are mounted above a package substrate including a substrate main body. First and second signal electrode pads are provided on a first main surface of the package substrate and are respectively joined to the first and second signal terminals. First and second outer terminals are provided on a second main surface 3b of the substrate main body. The first and second signal electrode pads and the first and second outer terminals are connected to each other with first and second wirings, respectively. The second outer terminal is located at the first signal electrode pad side and the first outer terminal is located at the second signal electrode pad side when seen from above.Type: ApplicationFiled: June 7, 2018Publication date: October 4, 2018Inventor: Toru TAKESHITA
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Publication number: 20170338797Abstract: In an electronic component, electrodes defining functional portions are provided on a piezoelectric substrate. In order to define a hollow portion which the functional portions face, there are provided a first support with a frame shape, and second supports on the piezoelectric substrate in an inner side region surrounded by the first support. A cover is laminated on the first support as well as on the second supports to define the hollow portion. A height of each of the second supports is higher than a height of the first support.Type: ApplicationFiled: August 10, 2017Publication date: November 23, 2017Inventor: Toru TAKESHITA
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Publication number: 20170317659Abstract: A surface acoustic wave device assembly includes a collective board, first circuit portions provided on the collective board and respectively including first hot terminals and first ground terminals, a second circuit portion provided on the collective board and including second hot terminals and second ground terminals, and a power supply wiring provided on the collective board so as to surround the periphery of the first circuit portions and the second circuit portion. The first circuit portions include surface acoustic wave devices defining band pass filters. The second circuit portion defines a band pass filter. The first ground terminals and first hot terminals, and the second ground terminal are connected to the power supply wiring, the second hot terminals are not connected to the power supply wiring, and pass bands of the surface acoustic wave devices and a pass band of the band pass filter defined by the second circuit portion are the same or substantially the same.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Toru TAKESHITA, Seiji KAI, Takashi NAKA, Motoji TSUDA, Mitsuyoshi HIRA
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Patent number: 7560236Abstract: The present invention provides a method which can enhance the precision of identification of bacterial species using a T-RFLP method and achieve, by itself, the identification of bacteria constituting a bacterial flora and the tracing of distribution changes thereof. The present invention provides a method for analyzing a bacterial community including: amplifying DNAs extracted from a bacterial community by PCR using 16S rRNA genes as templates and fluorescently labeled primers; cleaving the amplification products with a restriction enzyme to thereby obtain sample PCR fragments; electrophoresing the sample PCR fragments together with size standard PCR fragments; and comparing the mobilities thereof to thereby determine the sizes of the sample PCR fragments, wherein PCR fragments amplified by using, as a template, a 16S rRNA gene derived from a bacterium contained in the bacterial community to be analyzed are used as the size standards.Type: GrantFiled: June 7, 2007Date of Patent: July 14, 2009Assignee: Kao CorporationInventors: Yoshihisa Yamashita, Yoshio Nakano, Toru Takeshita
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Publication number: 20080305475Abstract: The present invention provides a method which can enhance the precision of identification of bacterial species using a T-RFLP method and achieve, by itself, the identification of bacteria constituting a bacterial flora and the tracing of distribution changes thereof. The present invention provides a method for analyzing a bacterial community including: amplifying DNAs extracted from a bacterial community by PCR using 16S rRNA genes as templates and fluorescently labeled primers; cleaving the amplification products with a restriction enzyme to thereby obtain sample PCR fragments; electrophoresing the sample PCR fragments together with size standard PCR fragments; and comparing the mobilities thereof to thereby determine the sizes of the sample PCR fragments, wherein PCR fragments amplified by using, as a template, a 16S rRNA gene derived from a bacterium contained in the bacterial community to be analyzed are used as the size standards.Type: ApplicationFiled: June 7, 2007Publication date: December 11, 2008Applicant: Kao CorporationInventors: Yoshihisa YAMASHITA, Yoshio Nakano, Toru Takeshita
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Patent number: 7184512Abstract: A clock generator is configured to generate, on the basis of an oscillation frequency clock of a voltage-controlled oscillator, a first signal having a phase the same as the oscillation frequency clock, a second signal having a phase delayed by a first phase amount to the first signal and a third signal having a phase delayed by a second phase amount to the first signal. A phase detection circuit is configured to provide a phase control on the basis of a phase difference between the third signal and an input signal. A frequency detection circuit is configured to sample the first and second signals synchronously with the input signal, thereby performing a frequency control for the voltage-controlled oscillator on the basis of the sampled signals.Type: GrantFiled: January 28, 2003Date of Patent: February 27, 2007Assignee: Sony CorporationInventors: Toru Takeshita, Takashi Nishimura
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Patent number: 6915081Abstract: The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, stabilized PLL operation is achieved. The PLL circuit includes a phase detection circuit and a frequency detection circuit. The frequency detection circuit includes a pair of D-type flip-flops for sampling first and second clock signals having different phases from each other in synchronism with an input signal at each rising or falling changing point of the input signal for each period, and a control logic circuit for logically operating the signals sampled by the D-type flip-flops and the signals sampled successively subsequently by the D-type flip-flops. The control logic circuit generates an UP pulse signal or a DOWN pulse signal based on a result of the arithmetic operation.Type: GrantFiled: October 17, 2001Date of Patent: July 5, 2005Assignee: Sony CorporationInventors: Toru Takeshita, Takashi Nishimura