Patents by Inventor Toru Tanzawa

Toru Tanzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatuses and methods for charging a global access line prior to accessing a memory
    Patent number: 10685721
    Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Segmented memory and operation
    Patent number: 10672477
    Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of series-connected memory cells of the plurality of strings of series-connected memory cells may be selectively connected to a common data line through a corresponding respective select gate, a first set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a second set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Toru Tanzawa, Han Zhao
  • APPARATUS AND METHODS INCLUDING ESTABLISHING A NEGATIVE BODY POTENTIAL IN A MEMORY CELL
    Publication number: 20200143894
    Abstract: Apparatus configured to establish a negative potential in a body of a memory cell during an access operation of another memory cell, and methods of operating such an apparatus, as well as apparatus configured to establish a negative potential in a body of a memory cell in response to a timer, or before a sensing operation of the memory cell.
    Type: Application
    Filed: September 18, 2019
    Publication date: May 7, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet
  • MEMORY DEVICE INCLUDING MIXED NON-VOLATILE MEMORY CELL TYPES
    Publication number: 20200133509
    Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.
    Type: Application
    Filed: December 26, 2019
    Publication date: April 30, 2020
    Inventor: Toru Tanzawa
  • RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES
    Publication number: 20200105352
    Abstract: Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Inventor: Toru Tanzawa
  • Memory read apparatus and methods
    Patent number: 10580502
    Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Semiconductor apparatus with multiple tiers, and methods
    Patent number: 10580790
    Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Field effect transistors having a fin
    Patent number: 10573728
    Abstract: Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • MEMORY HAVING MEMORY CELL STRING AND COUPLING COMPONENTS
    Publication number: 20200007896
    Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Inventor: Toru Tanzawa
  • Memory device including mixed non-volatile memory cell types
    Patent number: 10521130
    Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: December 31, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Random telegraph signal noise reduction scheme for semiconductor memories
    Patent number: 10510420
    Abstract: Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Connecting memory cells to a data line sequentially while applying a read voltage to the memory cells and programming the read data to a single memory cell
    Patent number: 10504599
    Abstract: Programming methods include programming first and second data in first and second memory cells, reading the first data from the first memory cell by applying a read voltage to an access line connected to the first and second memory cells while the first memory cell is electrically connected to a data line and while the second memory cell is electrically disconnected from the data line, reading the second data from the second memory cell by electrically disconnecting the first memory cell from the data line and electrically connecting the second memory cell to the data line while the read voltage remains applied to the access line, and programming the read first data and the read second data in a single memory cell connected to a different access line.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Ramin Ghodsi, Toru Tanzawa
  • Apparatuses and methods to control body potential in 3D non-volatile memory operations
    Patent number: 10490292
    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
  • Memory having memory cell string and coupling components
    Patent number: 10484718
    Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • FIELD EFFECT TRANSISTORS HAVING A FIN
    Publication number: 20190348529
    Abstract: Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 14, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Toru Tanzawa
  • Apparatus and methods including establishing a negative body potential in a memory cell
    Patent number: 10453538
    Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet
  • APPARATUSES AND METHODS FOR CHARGING A GLOBAL ACCESS LINE PRIOR TO ACCESSING A MEMORY
    Publication number: 20190318788
    Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: TORU TANZAWA
  • APPARATUSES AND METHODS FOR MEASURING AN ELECTRICAL CHARACTERISTIC OF A MODEL SIGNAL LINE AND PROVIDING MEASUREMENT INFORMATION
    Publication number: 20190286777
    Abstract: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Applicant: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • APPARATUSES AND METHODS INVOLVING ACCESSING DISTRIBUTED SUB-BLOCKS OF MEMORY CELLS
    Publication number: 20190279695
    Abstract: Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.
    Type: Application
    Filed: December 31, 2018
    Publication date: September 12, 2019
    Inventor: Toru Tanzawa
  • INTERCONNECTIONS FOR 3D MEMORY
    Publication number: 20190267047
    Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Inventor: Toru Tanzawa