Abstract: An encoded video data synthesis apparatus includes: a decoding unit having N, that is, two or more, decoders for decoding input encoded video data; an encoding unit having N encoders for encoding image data from the decoding unit; a buffer unit having N buffers which can store the encoded video data as a process result of the encoding unit for a predetermined number of frames; a stream synthesis unit for performing a synthesizing process on the encoded video data of one frame from each buffer; and a control unit for issuing an instruction to perform a synthesizing process to the stream synthesis unit. The encoded video data synthesis apparatus can further include a frame memory unit having N frame memory which can store a predetermined number of pieces of image data from a decoding unit between a decoding unit and an encoding unit.

Abstract: An optoelectronic apparatus includes an optoelectronic device, a mounting portion, a frame member surrounding a periphery of the mounting portion, and an optical component. The optical component is placed on an optical component placement portion. The frame member includes a pair of first side walls and a pair of second side walls. Each of the pair of second side walls has a recessed portion and a protruded portion. The optical component is disposed between the protruded portions, and is fixed with an adhesive filled in the recessed portions.

Abstract: A memory controller includes a memory unit having an n-byte memory data width, a register unit consecutively reading out, in response to an enable signal supplied thereto, data from the memory unit having n-byte size, the register unit further recording therein the data read out from the memory unit in the form of continuous data of 2n−1 bytes including the last data read out from the memory unit, a shifter unit selecting consecutively a block of continuous n-byte data from the continuous data of 2n−1 bytes recorded in the register unit, the shifter unit supplying the continuous n-byte data block to an output terminal, and a control unit controlling the memory unit, the register unit and the shifter unit.

Abstract: A parallel processor system is constructed to include a pair of parallel buses (2, 3), pipeline buses (9), a plurality of processor nodes (1-1 to 1-N) having functions of carrying out an operation process in response to an instruction and transferring data, cluster switches (5-1 to 5-N, 6-1 to 6-N, 7-1a to 7-La, 7-1b to 7-+b, 8-1a to 8-Ma, 8-1b to 8-(M−1)b) having a plurality of connection modes and controlling connections of the parallel buses, the pipeline buses and the processor nodes, and a switch controller (4) controlling the connection mode of the cluster switches and coupling the processor nodes in series and/or in parallel.

Abstract: A newspaper dealer server is provided with at least a contractor data base that registers contractors who have subscriber contracts with a newspaper dealer. An advertisement preparation unit of the server prepares an advertisement that is requested from an advertiser, and places it in an advertisement Web page. Upon finding that a user is a contractor on the contractor data base through an input of the user information, an advertisement utilization unit of the server publicizes the advertisement Web page and allows the user to view it.

Abstract: A processor architecture includes a program counter which executes M independent program streams in time division in units of one instruction, a pipeline which is shared by each of the program streams and has N pipeline stages operable at a frequency F, and a mechanism which executes only s program streams depending on a required operation performance, where M and N are integers greater than or equal to one and having no mutual dependency, s is an integer greater than or equal to zero and satisfying s≦M. An apparent number of pipeline stages viewed from each of the program streams is set to N/M so that M parallel processors having an apparent operating frequency F/M are formed.

Abstract: A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

Abstract: An optoelectronic apparatus includes an optoelectronic device, a mounting portion, a frame member surrounding a periphery of the mounting portion, and an optical component. The optical component is placed on an optical component placement portion. The frame member includes a pair of first side walls and a pair of second side walls. Each of the pair of second side walls has a recessed portion and a protruded portion. The optical component is disposed between the protruded portions, and is fixed with an adhesive filled in the recessed portions.

Abstract: A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

Abstract: The present invention relates to a multiprocessor system, which comprises two or more processor elements to be executed by a common program, a control section for switching such plural processor elements one from another for execution by the common program, and a storing section storing handover information relating to the common program which information is to be handover from the one processor element to the another processor element. This not only optimizes each of the functions of the processor elements, but also achieves certain delivery or interchange of the information between these process or elements, and even reduces the power consumption.

Abstract: To more precisely output signals of optical recording media, a semiconductor laser element is mounted in a concave portion on the surface of a semiconductor substrate so that the optical axis of signal detecting light emitted from the semiconductor laser element is substantially parallel to the surface of the semiconductor substrate, and the light emitted from the semiconductor laser element is reflected at the side surface of the concave portion that is opposed to the signal detecting light emitting side of the semiconductor laser element in a direction substantially perpendicular to the surface of the semiconductor substrate. A light receiving portion for signal detection is provided in an area outside the concave portion on the surface of the semiconductor substrate where the semiconductor laser element is mounted.

Abstract: An optoelectronic apparatus includes an optoelectronic device, a mounting portion, a frame member surrounding a periphery of the mounting portion, and an optical component. The optical component is placed on an optical component placement portion. The frame member includes a pair of first side walls and a pair of second side walls. Each of the pair of second side walls has a recessed portion and a protruded portion. The optical component is disposed between the protruded portions, and is fixed with an adhesive filled in the recessed portions.

Abstract: A processor is efficiently controlled and the electric power required to drive the processor is reduced by switching between a process of driving a plurality of arithmetic units using a series of instructions from an instruction control unit and a process of driving a plurality of arithmetic units using a plurality of series of instructions from different instruction control units according to an object to be processed. When a plurality of instruction control units 10, 11 and 12 drive a plurality of arithmetic units 13, 14 and 15, a synchronous execution process of driving the plurality of arithmetic units 13, 14 and 15 using the series of instructions from the first instruction control unit 10 is switched to/from an independent execution process of driving the arithmetic units 13, 14 and 15 using the series of instructions from the instruction control units 10, 11 and 12, respectively, according to the information contained in the series of instructions.

Abstract: An information processing apparatus is constructed to include a judging part for decoding an address of an input request and outputting a judgement signal which indicates whether the input request is a cache control request or a DMA control request, and a control part for carrying out a cache control when the judgement signal from the judging part indicates the cache control request, and carrying out a DMA control when the judgement signal indicates the DMA control request.

Abstract: A parallel processor system is constructed to include a pair of parallel buses (2, 3), pipeline buses (9), a plurality of processor nodes (1-1 to 1N) having functions of carrying out an operation process in response to an instruction and transferring data, cluster switches (5-1 to 5-N, 6-1 to 6-N, 7-1a to 7-La, 7-1b to 7-+b, 8-1a to 8-Ma, 8-1b to 8-(M-1)b) having a plurality of connection modes and controlling connections of the parallel buses, the pipeline buses and the processor nodes, and a switch controller (4) controlling the connection mode of the cluster switches and coupling the processor nodes in series and/or in parallel.

Abstract: A microprocessor capable of executing a process instruction having at least one RISC type instruction is constructed to include an instruction decoding section for decoding a microcode including information which indicates transfer contents of input and output data and address information which indicates a storage location of the process instruction, a data reading section for reading input data corresponding to the information which indicates the transfer contents of the input and output data decoded by the instruction decoding section and reading the process instruction corresponding to the address information, and an operation process executing section for implementing one or a plurality of operation unit resources capable of executing an operation process according to the input data read by the data reading section and the process instruction.

Abstract: An optoelectronic apparatus includes an optoelectronic device, a mounting portion, a frame member surrounding a periphery of the mounting portion, and an optical component. The optical component is placed on an optical component placement portion. The frame member includes a pair of first side walls and a pair of second side walls. Each of the pair of second side walls has a recessed portion and a protruded portion. The optical component is disposed between the protruded portions, and is fixed with an adhesive filled in the recessed portions.

Abstract: An object is that stray light carriers are absorbed, and hence a signal larger than actual signal will not be outputted, thereby to output more precise signals. For achieving the foregoing, a concave portion is provided on the surface of a semiconductor substrate, a light receiving element for signal detection is provided around the concave portion, a semiconductor laser element is mounted in the concave portion, and a light shielding area is provided on the side existing between the semiconductor laser element and the light receiving element for signal detection of the sides of the concave portion. This causes stray light contained in the light emitted from the semiconductor laser element to be cut off at the light shielding area. Consequently, around the light receiving element for signal detection, the occurrence of stray light carriers on the surface of the semiconductor substrate can be prevented, and hence the stray light carriers are not absorbed by the light receiving element for signal detection.