Patents by Inventor Toru Yamaoka

Toru Yamaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11939700
    Abstract: In various embodiments, single-crystal aluminum nitride boules and substrates are formed from the vapor phase with controlled levels of impurities such as carbon. Single-crystal aluminum nitride may be heat treated via quasi-isothermal annealing and controlled cooling to improve its ultraviolet absorption coefficient and/or Urbach energy.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: March 26, 2024
    Assignee: Crystal IS, Inc.
    Inventors: Robert T. Bondokov, James R. Grandusky, Jianfeng Chen, Shichao Wang, Toru Kimura, Thomas Miebach, Keisuke Yamaoka, Leo J. Schowalter
  • Patent number: 5946575
    Abstract: In a semiconductor integrated circuit device having a high breakdown voltage CMOS transistor integrated for programming a programmable element, the present invention is intended to solve a problem of the drain breakdown voltage of the high breakdown voltage transistor going low as a result of a structure that the standard transistor and the high breakdown voltage transistor share common channel dope region. On a P-type monocrystal silicon substrate of 10-20 .OMEGA.cm specific resistivity having a P-well region and a silicon oxide film for separating the elements, a channel dope region for an insulated-gate type field effect transistor A and a channel dope region for an insulated-gate type field effect transistor B are formed separately, making the impurity concentration in one channel dope region two to ten times as high as that in the other channel dope region.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: August 31, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Toru Yamaoka, Hirotsugu Honda, Hiroshi Sakurai
  • Patent number: 5913138
    Abstract: The present invention relates to the method of manufacturing an antifuse element having an antifuse layer formed between interconnection layers. Conventionally, an antifuse layer was formed after an aperture was formed through an interlayer insulating film. Such resulted in a thinner film thickness at the corner formed by inner wall surface of the aperture and a lower electrode layer. As it is very difficult to control the film thickness of the thinnest part to a specific value, control of the insulation breakdown voltage in "off" state was difficult. The present antifuse element includes a layer with a flat shape of an even thickness. The layer is a complexed film of amorphous silicon film, silicon nitride film and silicon oxide film. The antifuse electrode layer is of a titanium nitride, the film thickness of which is thicker than the invasion length of a fuse link into electrode layers.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: June 15, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Toru Yamaoka, Hiroshi Sakurai, Hirotsugu Honda, Hiroshi Yuasa