Abstract: An output circuit in accordance with one embodiment of the present invention includes: an input terminal for receiving an input signal; an output transistor connected between a first power supply and an output terminal; a current control circuit connected to the input terminal and the output transistor for controlling current outflow and inflow for the gate of the output transistor based on the input signal; a voltage generating circuit connected to the first power supply; and a switch circuit coupled between the gate of the output transistor and the voltage generating circuit, the switch circuit having alternatively an on state and an off state thereof in response to the input signal; wherein the switch circuit becomes the off state when the potential difference between the gate of the output transistor and the first power supply becomes equal to or below a predetermine value regardless of the voltage level of the input signal.

Abstract: An output circuit in accordance with one embodiment of the present invention includes: an input terminal for receiving an input signal; an output transistor connected between a first power supply and an output terminal; a current control circuit connected to the input terminal and the output transistor for controlling current outflow and inflow for the gate of the output transistor based on the input signal; a voltage generating circuit connected to the first power supply; and a switch circuit coupled between the gate of the output transistor and the voltage generating circuit, the switch circuit having alternatively an on state and an off state thereof in response to the input signal; wherein the switch circuit becomes the off state when the potential difference between the gate of the output transistor and the first power supply becomes equal to or below a predetermine value regardless of the voltage level of the input signal.

Abstract: A memory device is provided for reducing the test time and the complexity of the test pattern. The memory device is composed of a memory cell array including a plurality of memory cells, an I/O buffer, a command providing unit, an address providing unit, and an address decoder. The command providing unit is responsive to a test mode signal for providing a command that controls an access to the memory cell array. The address providing unit provides an address in response to the command. The address decoder allows the memory cell array to be accessed in response to the address. The command providing unit sets the command to be a predetermined internal command when the test mode signal is activated. The command providing unit, when the test mode signal is not activated, receives an external command through the I/O buffer and sets the command to be the external command.

Abstract: A memory device is provided for reducing the test time and the complexity of the test pattern. The memory device is composed of a memory cell array including a plurality of memory cells, an I/O buffer, a command providing unit, an address providing unit, and an address decoder. The command providing unit is responsive to a test mode signal for providing a command that controls an access to the memory cell array. The address providing unit provides an address in response to the command. The address decoder allows the memory cell array to be accessed in response to the address. The command providing unit sets the command to be a predetermined internal command when the test mode signal is activated. The command providing unit, when the test mode signal is not activated, receives an external command through the I/O buffer and sets the command to be the external command.

Abstract: A semicomductive memory device has a memory cell connected to a word line and a digit line. The memory cell is for memorizing data of two bits in correspondence to first through fourth threshold voltages. The first threshold voltage is lower than the second threshold voltage which is lower than the third threshold voltage. The third threshold voltage is lower than the fourth threshold voltage. The semicomductive memory device has a supplying section for selectively supplying first through third read-out voltages with the word line. The first read-out voltage has a value between the first and the second threshold voltages. The second read-out voltage has a value between the second and the third threshold voltages. The third read-out voltage has a value between the third and the second threshold voltages. The supplying section supplies the second read-out voltage to the word line at first.

Abstract: A semiconductor integrated circuit is provided, which decrease the circuit scale of an enabling circuit used for enabling and disabling an internal circuit. The enabling circuit has a first switching element with first and second terminals, a second switching element with first and second terminals, and a third switching element with first and second terminals. One of the first, second, and third switching elements is turned on and the remaining two ones thereof are turned off according to a program. The first terminal of the first switching element is applied with an enabling signal. The first terminal of the second switching element is applied with a disabling signal. The first terminal of the third switching element is applied with a Don't Care signal. The second terminals of the first, second, and third switching elements are connected in common to a node. One of the enabling signal, the disabling signal, and the Don't Care signal is selectively outputted to the node according to the program.