Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract: A data processor (1) includes a plurality of oscillation circuits (13 and 24) that individually generate a first clock signal (HCK) and a second clock signal (LCK) with a lower frequency, in which a CPU (10) performs data processing in synchronization with the oscillation output of an oscillation circuit selected by a clock switching circuit (22). In a state where the low power consumption mode is set, the data processor stops the first clock signal and maintains the oscillation of the second clock signal, selects whether or not to initiate the oscillation of the first clock signal in response to the trigger to cancel the low power consumption mode, and initiates the oscillation of the first clock signal without the CPU interrupt process which is enabled by the cancellation of the low power consumption mode.

Abstract: A header assembly includes a header holding a plurality of electrode pins to be insulated from one another, an ignition element mounting capacitor having at the center of its outer circumferential surfaces external terminal electrodes for electrically connecting to an ignition element mounted on the capacitor, an IC having first, second, and third electrode pads to be electrically connected to end electrodes of the ignition element mounting capacitor and the external terminal electrodes and further having connection electrodes to be electrically connected to the electrode pins of the header for communication with the external. The IC is located on the header, and the ignition element mounting capacitor is located on the IC and electrically connected to the electrode pins through the connection electrodes provided on the IC.

Abstract: An ignition element mounting capacitor having an ignition element mounted on a capacitor, includes therein a first capacitor section and a second capacitor section, and first external terminal electrodes electrically connected to the first capacitor section and second external terminal electrodes electrically connected to the second capacitor section. The first capacitor section has a capacity for igniting ignition powder, and the second capacitor section has a function for removing noise which affects external circuits. Further, provided on the surface of the capacitor are third external terminal electrodes electrically connected to the ignition element.

Abstract: An ignition element mounting capacitor having an ignition element mounted on a capacitor, includes therein a first capacitor section and a second capacitor section, and first external terminal electrodes electrically connected to the first capacitor section and second external terminal electrodes electrically connected to the second capacitor section. The first capacitor section has a capacity for igniting ignition powder, and the second capacitor section has a function for removing noise which affects external circuits. Further, provided on the surface of the capacitor are third external terminal electrodes electrically connected to the ignition element.

Abstract: A header assembly includes a header holding a plurality of electrode pins to be insulated from one another, an ignition element mounting capacitor having at the center of its outer circumferential surfaces external terminal electrodes for electrically connecting to an ignition element mounted on the capacitor, an IC having first, second, and third electrode pads to be electrically connected to end electrodes of the ignition element mounting capacitor and the external terminal electrodes and further having connection electrodes to be electrically connected to the electrode pins of the header for communication with the external. The IC is located on the header, and the ignition element mounting capacitor is located on the IC and electrically connected to the electrode pins through the connection electrodes provided on the IC.

Abstract: A housing for an impact printer has a case body and a cover thereof. They define therebetween an opening for the passage of the paper to be printed and the printed paper. A paper shelf lies over the top surface of the case body, and supported at one end rotatably away from the case body. The end of the paper shelf is located in the vicinity of the opening, and spaced apart from the case body and the cover only to the extent required for the passage of the paper to be printed and the printed paper. The top surface of the case body has at least one projection extending transversely of the paper to be printed. The paper shelf has a lower surface facing the top surface of the case body and formed with at least one projection extending transversely of the paper to be printed. This projection is spaced apart from the projection on the case body longitudinally of the paper to be printed.