Patents by Inventor Toshiaki Ichinose

Toshiaki Ichinose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040114099
    Abstract: In an eyeglasses to which the invention is applied, a taper nut having a collar portion and a conical taper portion is fitted and attached to a hole having a circular truncated cone shape and pierced in an eyeglasses part. A hole for passing a male screw therethrough is formed in another eyeglasses part, and the eyeglasses parts are connected to each other by screwing the male screw inserted to the hole with a female screw provided in an inner portion of the taper nut. Further, continuous holes having a circular truncated cone shape are pierced in both the connected eyeglasses parts. It is possible to prevent both the eyeglasses parts from rotating with each other by fitting the taper nut to the hole, and both the parts are connected by engaging the male screw from a side in which the taper of the taper nut is reduced.
    Type: Application
    Filed: January 20, 2004
    Publication date: June 17, 2004
    Inventors: Takeji Shiokawa, Mitsuya Mikawa, Toshiaki Ichinose, Yasuhisa Sunai, Masafumi Kamura
  • Patent number: 5463667
    Abstract: A method and an apparatus for inspecting a soldered joint with an X-ray, the soldered joint being formed by soldering a lead to a surface of a substrate.
    Type: Grant
    Filed: April 28, 1993
    Date of Patent: October 31, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Ichinose, Takanori Ninomiya, Asahiro Kuni, Kozo Nakahata, Toshimitsu Hamada, Toshihiko Ayabe
  • Patent number: 5278012
    Abstract: A method for producing a thin film multilayer substrate having a base substrate, and, which a plurality of conductor pattern layers superposed thereon through dielectric layers therebetween comprises the steps of: optically detecting the uppermost conductor pattern layer whenever the conductor pattern layer is formed on the base substrate; inspecting an absence and/or presence of a fault of the conductor pattern layer; and repairing a faulty portion in accordance with fault position data detected by the inspecting. According to this method, it is possible to enhance a production yield of relatively large size of thin film multilayer substrates which needs a relatively small amount of production at a high production cost, for mounting LSI chips thereon.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: January 11, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Chie Yamanaka, Toshiaki Ichinose, Takanori Ninomiya, Hisafumi Iwata, Yasuo Nakagawa, Nobuyuki Akiyama
  • Patent number: 4953224
    Abstract: A pattern defect detecting method and apparatus are disclosed on a connectivity processor to input a binary picture signal pattern and a pad position coordinate and outputting connectivity data between pads. Here, the connectivity processing refers to a processing for giving the identical number to one aggregation of connected or linked pads for the pads given to a serial pattern. In the connectivity processor wherein a plane on which the drawn pattern to be inspected is scanned by a linear sensor, the connectivity processing can be releazed almost concurrently with the scanning by driving a temporary memory.Also, a pattern defect detecting apparatus the above-mentioned connectivity. The invention processing coping with the difficulties of a required inspection level, and also represents a processing time of each embodiment theoretically. A moving time of the bed on which an inspecting object is placed and others are added to the real processing time.
    Type: Grant
    Filed: February 16, 1988
    Date of Patent: August 28, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Ichinose, Takanori Ninomiya, Yasuo Nakagawa
  • Patent number: 4860371
    Abstract: System for detecting pattern defects wherein images of corresponding portions of two originally identical patterns are detected and two image signals representing the images are registered with each other, a second image signal of the two registered signals is shifted by a predetermined number of pixels with respect to a first image signal, thus providing shifted second image signals. Differences in brightness between the first and second image signals as well as each of the shifted second image signals are calculated within intervals corresponding to pixels on one scanning line, thus providing a first group of difference image signals, preset values are added to and substracted from the first or second image signal to provide a sum image signal and a substraction image signal.
    Type: Grant
    Filed: July 22, 1987
    Date of Patent: August 22, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Yukio Matsuyama, Toshiaki Ichinose