Abstract: An encoder circuit comprising a plurality of input lines on each of which is to appear a logic "1" or "0" signal bit, a plurality of output lines, a first set of transistors of a first conductivity type, each of the first set transistors having a control terminal connected to each of the input lines and input and output terminals connected between each of the output lines and a supply voltage source, a second set of transistors of a second conductivity type opposite to the first conductivity type, each of the second set transistors having a control terminal connected to each of the input lines and input and output terminals between each of the output lines and ground, and a plurality of logic inverter devices each connected between each of the input lines and each of the transistors of one of the first and second conductivity types.

Abstract: A bidirectional barrel shift circuit includes an input switching circuit having a plurality of parallel input lines and the corresponding number of first and second signal line pairs associated to the respective input lines. This input switching circuit is operative to selectively connect each of the input lines to one line of the associated first and second signal line pair. There is also provided an output switching circuit connected to all the first and second singal lines and having output lines of the number corresponding to that of the input lines. This output switching circuit is operative to connect either the first signal lines or the second signal lines to the corresponding output lines. A barrel shift matrix is connected to the first and second signal lines and is controlled by a shift number controller so as to produce between the first and second signal lines a connection pattern sufficient for realizing a given shift number.

Abstract: In a Booth's algorithm multiplication circuit, a multiplicand is set in a multiplication register and a multiplier is set in a multiplier shift-register. Consecutive bits of the multiplier are applied to a Booth's decoder to produce coefficients, and the multiplicand and coefficient are multiplied by each other to produce a partial product. Partial products are produced for every three consecutive bits of the multiplier, and the obtained partial products are added to the sum of previously obtained partial products. After all the partial products are added together, the resultant sum is derived from the adder or from the feed-back path of the output from the adder.