Patents by Inventor Toshiaki Nagase

Toshiaki Nagase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090283765
    Abstract: A semiconductor unit includes a semiconductor chip, a ceramic substrate having a circuit pattern on which the semiconductor chip is mounted, and a temperature sensor for detecting a temperature. The semiconductor unit further includes a pressing member for retaining the temperature sensor by pressing against the ceramic substrate.
    Type: Application
    Filed: May 13, 2009
    Publication date: November 19, 2009
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Hiroyuki Onishi, Toshiaki Nagase, Jun Ishikawa, Kazuyoshi Kontani, Toshinari Fukatsu
  • Publication number: 20090257211
    Abstract: A power converter apparatus that includes a substrate, plate-like positive and negative interconnection members, capacitors, and a cover is disclosed. Pairs of groups of switching elements are mounted on the substrate. The cover is arranged over the substrate to encompass the switching elements, the positive interconnection member, the negative interconnection member, and the capacitor. The positive interconnection member and the negative interconnection member each have a terminal portion that is joined to a circuit pattern on the substrate by ultrasonic bonding.
    Type: Application
    Filed: March 4, 2009
    Publication date: October 15, 2009
    Applicant: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Kazuyoshi Kontani, Toshinari Fukatsu, Toshiaki Nagase, Hiroyuki Onishi, Jun Ishikawa
  • Publication number: 20090251875
    Abstract: A power converter apparatus that includes a substrate, plate-like positive and negative interconnection members, and capacitors is disclosed. Pairs of groups of switching elements are mounted on the substrate. Each of the positive interconnection member and the negative interconnection member has a terminal portion. The terminal portion has a joint portion that is electrically joined to a circuit pattern on the substrate. The switching elements are arranged in the same number on both sides of the joint portion of at least the positive interconnection member of the positive and negative interconnection members.
    Type: Application
    Filed: March 3, 2009
    Publication date: October 8, 2009
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Takashi Nagashima, Hiroyuki Onishi, Toshiaki Nagase, Jun Ishikawa, Kazuyoshi Kontani, Toshinari Fukatsu
  • Publication number: 20090237904
    Abstract: A power converter apparatus includes a substrate 22 on which switching elements Q, Q1 to Q6 are mounted, positive and negative terminal interconnection members 27, 28 mounted on the substrate, and a capacitor 17 having a positive terminal 17a connected to the main body of the positive terminal interconnection member 27 and a negative terminal 17b connected to the main body of the negative terminal interconnection member 28. The interconnection members each have a plate-like main body 27a, 28a that is located above and parallel to the substrate 22. The main bodies of the interconnection members are stacked to be close to each other while being electrically insulated from each other. Each of the positive terminal interconnection member and the negative terminal interconnection member further includes a plate-like extension 27b, 28b that extends from the corresponding main body toward the substrate, and a terminal portion 27c, 28c that extends from the extension and is joined to the substrate.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 24, 2009
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Hiroyuki Onishi, Toshiaki Nagase, Jun Ishikawa, Kazuyoshi Kontani, Toshinari Fukatsu, Hiroyuki Kobayashi, Naohito Kanie, Takahiro Nakamura
  • Publication number: 20090225523
    Abstract: An electronic unit includes a first circuit board having a power semiconductor device and an electrolytic capacitor and a second circuit board having an electronic component to control the power semiconductor device. The second circuit board is arranged perpendicular to the first circuit board and along the surface of the electrolytic capacitor. The electronic unit further includes a connecting member being jointed at one end thereof to the first circuit board and jointed at the other end thereof to the second circuit board for electrical connection between the first and second circuit boards.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 10, 2009
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Hiroyuki Onishi, Toshiaki Nagase, Jun Ishikawa, Naohito Kanie, Kazuyoshi Kontani
  • Publication number: 20090225577
    Abstract: A power converter includes a base plate having thereon a switching device, and positive and negative conductors respectively including main portions disposed parallel to the base plate. One of the main portions is placed over the other of the main portions. The main portions are disposed adjacent to and parallel to each other. The main portions are insulated from each other. The power converter includes a capacitor having positive and negative terminals electrically connected to the respective main portions of the positive and negative conductors. Each of the positive and negative conductors includes a side portion extending from the main portion toward the base plate, and a terminal portion extending from the side portion and joined to the base plate. The side portion is formed with a cutout extending from the end adjacent to the base plate to the opposite end connected to the main portion.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 10, 2009
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Hiroyuki Onishi, Toshiaki Nagase, Jun Ishikawa, Kazuyoshi Kontani, Toshinari Fukatsu
  • Patent number: 7397116
    Abstract: A semiconductor apparatus is characterized in that it comprises a semiconductor module having a plurality of semiconductor elements and an external connection terminal for externally connecting electrodes of the semiconductor elements in the semiconductor module, wherein the semiconductor elements in each semiconductor module are connected in parallel and/or in series via the external connection terminal.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: July 8, 2008
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Hiroyuki Onishi, Toshiaki Nagase, Jun Ishikawa, Koichi Akagawa
  • Patent number: 7256489
    Abstract: In a semiconductor apparatus in which a main current of a semiconductor device flows through a wiring pattern formed on an insulation circuit board, the rise in temperature of the wiring pattern is suppressed and the increase in cost of parts can be minimized. On the insulation circuit board, a copper pattern is formed. A heat spreader is soldered to the copper pattern, and the heat spreader is loaded with a semiconductor chip. An external electrode and the heat spreader are arranged to shorten the distance between the side of the external electrode and the side of the heat spreader.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: August 14, 2007
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Jun Ishikawa, Toshiaki Nagase, Hiroyuki Onishi, Koichi Akagawa
  • Publication number: 20060255448
    Abstract: A first wiring member and a second wiring member, through which currents flow in directions opposite to each other, each have a flat plate shape and are arranged to be adjacent and opposed to each other, to thereby reduce inductances of the first wiring member and the second wiring member due to an effect of a mutual inductance. A joint of the first wiring member and a joint of the second wiring member are joined to the positive terminal and the negative terminal of the semiconductor device through ultrasonic bonding, respectively. As a result, the joint of the first wiring member and the joint of the second wiring member are not required to be provided with exclusive portions for screw mounting unlike a conventional manner, so each of the joints can have a small area, to thereby making it possible to reduce inductances of the first wiring member and the second wiring member.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 16, 2006
    Inventors: Toshiaki Nagase, Hiroyuki Onishi, Jun Ishikawa
  • Patent number: 7091580
    Abstract: When a silicone gel is injected into a case, since the gel is liquid before curing, the gel attempts to rise along a minute gap formed between a front face of a first electrode and a rear face of a resin member due to capillary action. However, since the gap becomes larger at a cavity in the first electrode, the rising motion of the gel stops at the level of the cavity. More specifically, the gel is prevented from reaching portions of the first electrode and a second electrode for connection with external terminals. Further, since the rising motion of the gel can be prevented by the cavity, the first electrode and the second electrode can be arranged in a close relationship with each other.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Koichi Akagawa, Toshiaki Nagase, Hiroyuki Onishi, Jun Ishikawa
  • Publication number: 20050151167
    Abstract: A semiconductor apparatus is characterized in that it comprises a semiconductor module having a plurality of semiconductor elements and an external connection terminal for externally connecting electrodes of the semiconductor elements in the semiconductor module, wherein the semiconductor elements in each semiconductor module are connected in parallel and/or in series via the external connection terminal.
    Type: Application
    Filed: January 4, 2005
    Publication date: July 14, 2005
    Inventors: Hiroyuki Onishi, Toshiaki Nagase, Jun Ishikawa, Koichi Akagawa
  • Publication number: 20050104189
    Abstract: When a silicone gel is injected into a case, since the gel is liquid before curing, the gel attempts to rise along a minute gap formed between a front face of a first electrode and a rear face of a resin member due to capillary action. However, since the gap becomes larger at a cavity in the first electrode, the rising motion of the gel stops at the level of the cavity. More specifically, the gel is prevented from reaching portions of the first electrode and a second electrode for connection with external terminals. Further, since the rising motion of the gel can be prevented by the cavity, the first electrode and the second electrode can be arranged in a close relationship with each other.
    Type: Application
    Filed: October 12, 2004
    Publication date: May 19, 2005
    Inventors: Koichi Akagawa, Toshiaki Nagase, Hiroyuki Onishi, Jun Ishikawa
  • Publication number: 20050093137
    Abstract: In a semiconductor apparatus in which a main current of a semiconductor device flows through a wiring pattern formed on an insulation circuit board, the rise in temperature of the wiring pattern is suppressed and the increase in cost of parts can be minimized. On the insulation circuit board, a copper pattern is formed. A heat spreader is soldered to the copper pattern, and the heat spreader is loaded with a semiconductor chip. An external electrode and the heat spreader are arranged to shorten the distance between the side of the external electrode and the side of the heat spreader.
    Type: Application
    Filed: November 2, 2004
    Publication date: May 5, 2005
    Inventors: Jun Ishikawa, Toshiaki Nagase, Hiroyuki Onishi, Koichi Akagawa
  • Patent number: 6566750
    Abstract: A plurality of semiconductor chips are provided on a base substrate. A drain region of the respective semiconductor chip is directly connected to the base substrate. A source electrode is formed in parallel with the arranging direction of the plurality of semiconductor chips. A source electrode and a source region of the respective semiconductor chip are connected using bonding wires. A plurality of source terminals are connected to the source electrode. A plurality of drain terminals are connected to the base substrate. The source terminal and drain terminal are located close to one another.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: May 20, 2003
    Assignee: Kabushiki Kaisha Toyoda Jidoshokki Seisakusho
    Inventors: Kenichi Sofue, Hiromitsu Yoshiyama, Toshinari Fukatsu, Toshiaki Nagase
  • Patent number: 6445068
    Abstract: A plurality of MOS transistors are arranged on the top surface of a conductor substrate which is a drain electrode. The drain contact of each MOS transistor is connected to the conductor substrate. The source contact of each MOS transistor is connected to the output conductor path which is a source electrode through a bonding wire. The gate contact of each MOS transistor is connected to a drive signal conductor path which is a gate electrode through a bonding wire. The source contacts of the MOS transistors are interconnected through a bridge electrode and a bonding wire.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: September 3, 2002
    Assignee: Kabushiki Kaisha Toyoda Jidoshokki Seisakusho
    Inventors: Kenichi Sofue, Hiromitsu Yoshiyama, Toshinari Fukatsu, Toshiaki Nagase
  • Patent number: 6380617
    Abstract: The side of one of the source electrodes 7a and 7b of two semiconductor modules Q1 and Q2 corresponding to a pair of upper and lower arms are installed parallel with the outer side of the other source electrode inside packages 8a and 8b. Both the modules are arranged parallel to one another in such a way that both the sides are opposed, an inter-module electrode terminal 15 for connecting the source electrode 7a of the module Q1 and the drain electrode (base substrate) 6b of the module Q2 is formed in a block shape, and one end of the inter-module electrode terminal 15 is vertically installed parallel and close to the side of the source electrode 7b on the base substrate of the module Q2.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: April 30, 2002
    Assignee: Kabushiki Kaisha Toyoda Jidoshokki Seisakusho
    Inventors: Kenichi Sofue, Hiromitsu Yoshiyama, Toshinari Fukatsu, Toshiaki Nagase
  • Patent number: 6232654
    Abstract: A semiconductor module includes a MOSFET chip and a package for accommodating the MOSFET chip. The drain area of the MOSFET chip is connected to a base substrate. A source and a gate electrode are arranged on the top of the package, and also a drain electrode to be connected to the base substrate is arranged. On a printed-circuit board, to which a protection circuit is implemented, holes corresponding to the drain electrode, the source electrode, and the gate electrode are formed. The protection circuit is attached to the semiconductor module while the electrodes penetrate into the respective holes.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: May 15, 2001
    Assignee: Kabushiki Kaisha Toyoda Jidoshokki Seisakusho
    Inventor: Toshiaki Nagase
  • Patent number: D441726
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: May 8, 2001
    Assignee: Kabushiki Kaisha Toyoda Jidoshokki Seisakusho
    Inventors: Kenichi Sofue, Hiromitsu Yoshiyama, Toshinari Fukatsu, Toshiaki Nagase, Jun Ishikawa
  • Patent number: D443253
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: June 5, 2001
    Assignee: Kabushiki Kaisha Toyoda Jidoshokki Seisakusho
    Inventors: Toshiaki Nagase, Jun Ishikawa