Abstract: A cell stack management system includes a cell monitoring unit that measures an output voltage of a plurality of power storage cells, a battery management unit that manages a cell stack, and a first communication network that connects the cell monitoring unit and the battery management unit. The battery management unit includes: a first communication circuit connected to the first communication network; a second communication circuit connected to a second communication network for connecting to a higher-level system; a control circuit that controls the battery management unit; and a control circuit power supply. The cell stack management system includes a normal mode and a low-power mode as modes of operation. During transition from the low-power mode to the normal mode, the first communication circuit activates at least one of the control circuit power supply, the control circuit, or the second communication circuit.

Abstract: A DLL circuit includes: a time difference amplifier circuit that includes current sources for setting a time difference amplification factor and an input time difference range, and amplifies, to a first signal and a second signal which are input, a time difference between edges which are change points of logic levels respectively included in the first and second signals, using the current sources and outputting a first amplified signal and a second amplified signal obtained; a phase comparison circuit that calculates a phase difference between the first and second amplified signals output and outputs a phase difference signal indicating the phase difference calculated; and a variable delay circuit that delays the second signal by an amount of delay depending on the phase difference indicated by the phase difference signal output from the phase comparison circuit and outputs the delayed second signal as a delayed signal.

Abstract: A distance-measuring imaging device includes: a timing controller that outputs one or more timing signals; a light receiver that receives reflected light that is light emitted by a light source and reflected by a subject; a phase adjustment circuit that outputs at least one signal out of a light emission control signal and an exposure control signal, based on the one or more timing signals, the light emission control signal being used for causing the light source to emit light to the subject, the exposure control signal being used for causing the light receiver to start exposure. The phase adjustment circuit includes one or more DLL circuits each of which determines, for at least one of the one or more timing signals, at least one of a phase of a rising edge or a phase of a falling edge of the at least one signal.

Abstract: The present disclosure provides a vibration power generation device capable of generating large electric power relative to an amount of displacement of a portion of a specimen. Vibration power generation device according to the present invention includes piezoelectric part and displacement enhancer. In response to displacement of a portion of specimen, displacement enhancer displaces a portion of piezoelectric part by a displacement amount greater than an amount of the displacement of the portion of specimen. When the portion of piezoelectric part is displaced, piezoelectric part generates electric power in accordance with an amount of the displacement of the portion of piezoelectric part.

Abstract: A differential amplifier circuit comprises: first and second input terminals; first and second output terminals; a first transistor comprising a gate terminal connected to the first input terminal; a second transistor comprising a gate terminal connected to the second input terminal; a first resistor connected between the source terminal of the first transistor and the source terminal of the second transistor; a third transistor comprising a drain terminal connected to the source terminal of the first transistor, a gate terminal connected to the drain terminal of the first transistor, and a source terminal connected to the first output terminal; a fourth transistor comprising a drain terminal connected to the source terminal of the second transistor, a gate terminal connected to the drain terminal of the second transistor, and a source terminal connected to the second output terminal; first to fourth current sources; and second and third resistors.

Abstract: A differential amplifier circuit comprises: first and second input terminals; first and second output terminals; a first transistor comprising a gate terminal connected to the first input terminal; a second transistor comprising a gate terminal connected to the second input terminal; a first resistor connected between the source terminal of the first transistor and the source terminal of the second transistor; a third transistor comprising a drain terminal connected to the source terminal of the first transistor, a gate terminal connected to the drain terminal of the first transistor, and a source terminal connected to the first output terminal; a fourth transistor comprising a drain terminal connected to the source terminal of the second transistor, a gate terminal connected to the drain terminal of the second transistor, and a source terminal connected to the second output terminal; first to fourth current sources; and second and third resistors.

Abstract: An A/D converter includes: an input buffer; N sub-A/D converters including N first sampling circuits that are connected to the input buffer, and that sample the output analog signal in respective sampling slots; a control circuit that executes calibration for the N first sampling circuits one by one; a reference A/D converter including a second sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and a third sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N?1) first sampling circuits out of the execution of the calibration.

Abstract: A time-interleaved analog-to-digital (AD) converter includes: N AD converters; a frequency divider that receives a clock signal and applies 1/N frequency division N to the received clock signal to generate N frequency-divided clock signals to be supplied to the N AD converters; at least (N?1) variable delay circuit that adjusts delay time for at least (N?1) frequency-divided clock signal; a low pass filter circuit or an input buffer circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal; and a control circuit that controls the delay time of the at least (N?1) variable delay circuit, and decreases one or more differences among digital output values output from the N AD converters when the reference signal is input to the N AD converters.

Abstract: A time-interleaved analog-to-digital (AD) converter includes: N AD converters; a frequency divider that receives a clock signal and applies 1/N frequency division N to the received clock signal to generate N frequency-divided clock signals to be supplied to the N AD converters; at least (N?1) variable delay circuit that adjusts delay time for at least (N?1) frequency-divided clock signal; a low pass filter circuit or an input buffer circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal; and a control circuit that controls the delay time of the at least (N?1) variable delay circuit, and decreases one or more differences among digital output values output from the N AD converters when the reference signal is input to the N AD converters.

Abstract: An A/D converter includes: an input buffer; N sub-A/D converters including N first sampling circuits that are connected to the input buffer, and that sample the output analog signal in respective sampling slots; a control circuit that executes calibration for the N first sampling circuits one by one; a reference A/D converter including a second sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and a third sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N?1) first sampling circuits out of the execution of the calibration.

Abstract: A graphite spheroidizing agent containing: 30-80 wt % of Si; Mg; RE (rare earth element) which comprises Ce with a purity level of 80-100 wt % or La with a purity level of 80-100 wt %; Ca; and Al is used. The graphite spheroidizing agent is added so as to satisfy the conditions that an amount of RE equivalent to 0.001-0.009 wt % of the total weight of the molten metal, an amount of Ca equivalent to 0.001-0.02 wt % of the total weight of the molten metal, and an amount of Al equivalent to 0.001-0.02 wt % of the total weight of the molten metal are added to the molten metal, and that the molten metal contains 0.03-0.07 wt % of Mg after the graphite spheroidizing treatment. It is possible to suppress crystallization of chunky graphite in a thick section of spheroidal graphite cast iron and deterioration of mechanical properties, with a low cost.

Abstract: A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Abstract: A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Abstract: In one embodiment, a direct-contact steam condenser includes: a steam cooling chamber; a inflow part; a plurality of first spray nozzles; and a water reservoir part. The inflow part leads turbine exhaust gas containing steam and non-condensable gas in a substantially horizontal direction into the steam cooling chamber. The plurality of first spray nozzles are disposed in the steam cooling chamber to be connected to a plurality of spray pipes extending along the direction in which the turbine exhaust gas is led in, and spray cooling water to the turbine exhaust gas. The water reservoir part is disposed under the steam cooling chamber to store condensate water that is condensed from the steam by the spraying of the cooling water.

Abstract: In a differential amplifier, input terminals to which a differential input is given are connected to gates of input transistors, respectively. One ends of capacitive devices are connected to sources of the input transistors, respectively. A switching section switches connection between the other ends of the capacitive devices and the input terminals according to a control clock at each phase.

Abstract: A semiconductor integrated circuit according to the present invention is equipped with a plurality of analog macros having comb capacitors (10), each comb capacitor (10) has a comb-shaped first electrode (11) and a comb-shaped second electrode (12), comb tooth portions (13) of the electrode (11) and comb tooth portions (14) of the electrode (12) are engaged so that the comb tooth portions (13) and the comb tooth portions (14) are arranged alternately and parallel to one another, and a comb tooth interval S of the comb capacitor is varied according to an absolute accuracy indicating an error between an actual capacitance value and an ideal capacitance value, or a relative accuracy indicating a difference in capacitance values between adjacent comb capacitors. Thereby, it is possible to provide a semiconductor integrated circuit which is equipped with highly-accurate analog macros and highly-integrated analog macros having comb capacitors which ensure high capacitance accuracies.

Abstract: An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters. The A/D converter sets plural unit A/D converters performing parallel processings according to a system request, such that, when the A/D converter operates with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter is halted by a control signal, thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

Abstract: An analog switch (100) of the present invention is characterized by being constructed by MOS transistors and comprising a switch (102) connecting an input terminal VIN(104) and the substrate voltage of the NMOS transistor (101), a switch (103), being operated in a reverse phase to that of the switch (102), connecting the substrate voltage of the NMOS transistor(101) and the ground (VSS), and a voltage follower circuit (106) which, having a high input impedance and being connected between the input terminal (104) and the switch (102), suppresses the flow of the input current from the input terminal (104). According to the present invention, in an analog switch which is constituted by MOS transistors, it is possible to suppress that the input current flows into the substrate when the analog switch repeats the ON state and the OFF state.

Abstract: In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.

Abstract: In one embodiment, a direct-contact steam condenser includes: a steam cooling chamber; a inflow part; a plurality of first spray nozzles; and a water reservoir part. The inflow part leads turbine exhaust gas containing steam and non-condensable gas in a substantially horizontal direction into the steam cooling chamber. The plurality of first spray nozzles are disposed in the steam cooling chamber to be connected to a plurality of spray pipes extending along the direction in which the turbine exhaust gas is led in, and spray cooling water to the turbine exhaust gas. The water reservoir part is disposed under the steam cooling chamber to store condensate water that is condensed from the steam by the spraying of the cooling water.