Abstract: An electronic device includes a display having a number of pixels, source driving circuitry that drives data to the pixels, and data lines that communicatively couple the source driving circuitry with the pixels. The electronic device also includes quality monitoring and calibration circuitry that identifies degradation in the source driving circuitry, one or more of the data lines, or both. The electronic device may be controlled based at least in part upon identification of the degradation.

Abstract: To provide a resin composition having excellent mechanical strength and elongation, its melt-kneaded product and a molding product thereof. A resin composition comprising a fluororesin having a hydroxy group or a carbonyl group, an ester bond-containing resin having no fluorine atom and a transesterification catalyst, a melt-kneaded product obtained by melt-kneading the resin composition, a molding product, film or sheet obtained from the resin composition or the melt-kneaded product, a laminated product, a backsheet for a solar cell, and a method for producing a molding product using the resin composition or the melt-kneaded product.

Abstract: An electronic device includes a display having a number of pixels, source driving circuitry that drives data to the pixels, and data lines that communicatively couple the source driving circuitry with the pixels. The electronic device also includes quality monitoring and calibration circuitry that identifies degradation in the source driving circuitry, one or more of the data lines, or both. The electronic device may be controlled based at least in part upon identification of the degradation.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: To provide a resin composition having excellent mechanical strength and elongation, its melt-kneaded product and a molding product thereof. A resin composition comprising a fluororesin having a hydroxy group or a carbonyl group, an ester bond-containing resin having no fluorine atom and a transesterification catalyst, a melt-kneaded product obtained by melt-kneading the resin composition, a molding product, film or sheet obtained from the resin composition or the melt-kneaded product, a laminated product, a backsheet for a solar cell, and a method for producing a molding product using the resin composition or the melt-kneaded product.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: There is provided a fly sewing machine. A fly supply unit is configured to supply flies to a transfer passage. A fly transfer unit is configured to transfer and send the fly supplied by the fly supply unit toward the downstream side thereof. A chain feed unit is configured to feed a slide fastener chain onto the flies sent by the fly transfer unit. An auxiliary conveyance unit is configured to press the flies and the slide fastener chain which are overlapped by the chain feed unit from above or below, and to send the flies and the slide fastener chain toward the downstream side thereof. A sewing machine part is configured to stitch together the flies and the slide fastener chain sent by the auxiliary conveyance unit.

Abstract: To provide a polymer composition containing an ethylene/tetrafluoroethylene copolymer, which is excellent in elongation, a molded product thereof, a film and a backsheet for a solar cell. A polymer composition comprising an ethylene/tetrafluoroethylene copolymer, a poly(meth)acrylate and a fluoroelastomer; a molded product made of such a composition; a method for producing such a molded product; and a backsheet for a solar cell, which contains a film made of the polymer composition.

Abstract: To provide a blended polymer containing an ethylene/tetrafluoroethylene copolymer, which is excellent in weather resistance and has a high thermal deformation temperature, a molded product such as a film thereof, a back sheet for a solar cell provided with such a film, etc., and a method for producing such a molded product. A blended polymer which comprises an ethylene/tetrafluoroethylene copolymer and a polymethyl methacrylate, wherein the mass ratio of the ethylene/tetrafluoroethylene copolymer to the total mass of the ethylene/tetrafluoroethylene copolymer and the polymethyl methacrylate, is from 50 to 75%, and which has a microphase-separated structure wherein the continuous phase is the ethylene/tetrafluoroethylene copolymer, and the dispersed phase is the polymethyl methacrylate.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern Pib is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: There is provided a fly sewing machine. A fly supply unit is configured to supply flies to a transfer passage. A fly transfer unit is configured to transfer and send the fly supplied by the fly supply unit toward the downstream side thereof. A chain feed unit is configured to feed a slide fastener chain onto the flies sent by the fly transfer unit. An auxiliary conveyance unit is configured to press the flies and the slide fastener chain which are overlapped by the chain feed unit from above or below, and to send the flies and the slide fastener chain toward the downstream side thereof. A sewing machine part is configured to stitch together the flies and the slide fastener chain sent by the auxiliary conveyance unit.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.