Abstract: In an LSI design method of designing a clock tree that supplies a clock signal to a plurality of leaves from a clock supply point, when a high level clock tree is constituted by H-tree and a low level clock tree is formed by CTS, the number of stages of a high level clock tree is optimized without giving any constraint on the placement of a low level clock tree. The leaves are divided into a plurality of groups to form a low level local tree. A clock-supplied region including all leaves to be supplied with a clock is uniformly divided and for each divided region, a skew when a clock signal is supplied from an end of an H-tree to start points of a plurality of local trees included in that region is estimated. The clock-supplied region is more finely equally-divided to increase the number of stages of H-tree.

Abstract: In an LSI design method of designing a clock tree that supplies a clock signal to a plurality of leaves from a clock supply point, when a high level clock tree is constituted by H-tree and a low level clock tree is formed by CTS, the number of stages of a high level clock tree is optimized without giving any constraint on the placement of a low level clock tree. The leaves are divided into a plurality of groups to form a low level local tree. A clock-supplied region including all leaves to be supplied with a clock is uniformly divided and for each divided region, a skew when a clock signal is supplied from an end of an H-tree to start points of a plurality of local trees included in that region is estimated. The clock-supplied region is more finely equally-divided to increase the number of stages of H-tree.

Abstract: A method of designing a semiconductor device is provided. According to the method, a group of cells that is a target of clock distribution is placed. After the group of cells is placed, a plurality of clock driver cells for driving the clock are placed such that each clock driver cell is prohibited from overlapping with a prohibited region of a predetermined size surrounding another clock driver cell.

Abstract: A semiconductor integrated circuit 1 according to an exemplary embodiment of the present invention is including: a first wire that is supplied with a clock signal; a second wire that is supplied with the clock signal, the clock signal is supplied or shut off independently of the clock signal supplied to the first wire; a first area that includes a first mesh shape wire supplied with the clock signal from the first wire; a second area that includes a second mesh shape wire supplied with the clock signal from the second wire; and a switching circuit that switches to a conduction or a shutoff of a signal transmitted between the first mesh shape wire and the second mesh shape wire.

Abstract: Power wiring comprises a first-layer power wiring cluster in which VDD wiring trace and VSS wiring trace of different potentials at single trace width are arranged alternatingly; a second-layer power wiring cluster, disposed in a layer overlying the first-layer power wiring cluster, in which a VDD wiring trace and a VSS wiring trace of different potentials at single trace width are arranged alternatingly; and vias, placed in areas where the first-layer power wiring cluster and second-layer power wiring clusters intersect three-dimensionally, for electrically connecting wiring traces of the same potential in the first-layer power wiring cluster and wiring traces of the same potential in the second-layer power wiring cluster. A signal-wiring formation area is provided between mutually adjacent first-layer power wiring clusters and between mutually adjacent second-layer power wiring clusters. Design rule violation regarding via density is avoided without decline in integration or an increase in chip area.

Abstract: A method of designing a semiconductor device is provided. According to the method, a group of cells that is a target of clock distribution is placed. After the group of cells is placed, a plurality of clock driver cells for driving the clock are placed such that each clock driver cell is prohibited from overlapping with a prohibited region of a predetermined size surrounding another clock driver cell.