Patents by Inventor Toshiaki Usui

Toshiaki Usui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080068249
    Abstract: A housing has an electric opening in a position corresponding to the radar. A shielding plate is provided between the radar and the electric opening and has an opening including a plurality of unit openings in a position corresponding to the radar. The unit openings satisfy a relation (half-wave length of radio wave that should be shielded)>(maximum dimension “r” of the unit openings)>(half-wave length of radio wave transmitted by the radar). An opening ratio “s” is set to satisfy a relation ((power amount of the transmission wave of the radar)?(attenuated power amount of the transmission wave of the radar))>(the threshold of the radar)>(power amount of the reflected wave at the shielding plate).
    Type: Application
    Filed: September 27, 2007
    Publication date: March 20, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Yutaka Yaginuma, Hiroshi Ogura, Yutaka Moriyama, Toshiaki Usui, Masaaki Mikuni
  • Patent number: 5896180
    Abstract: A phase-locked loop circuit generates a clock signal synchronized with a color burst signal contained in a composite color picture signal. The phase-locked loop circuit contains a phase synchronization loop having a loop gain, extracts the color burst signal from the composite color picture signal, compares the phases of the generated clock signal and the color burst signal, and controls the phase of the generated clock signal to reduce the difference between the above phases. The phase-locked loop circuit further detects the vertical blanking signal, and reduces the loop gain for the duration of the vertical blanking signal. Alternatively, a horizontal synchronizing signal is used instead of the color burst signal. Another phase-locked loop circuit generates a clock signal synchronized with a reference clock signal based on first frequency information indicating a frequency of the reference clock signal.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: April 20, 1999
    Assignee: Fujitsu Limited
    Inventor: Toshiaki Usui
  • Patent number: 5684527
    Abstract: In a multipoint videoconferencing system including a plurality of visual telephone terminals and a multipoint control unit (MCU) connected thereto, shares of the respective visual telephone terminals are determined in the MCU, based on determination of a speaker determined from voice levels and/or amount of movement in the respective visual telephone terminals. The respective telephone terminals generate pictures at picture rates defined by the respective shares, and generate video data from the pictures at data rates defined by the respective shares. Video data generated in each visual telephone terminal are multiplexed in time division multiplexer in the MCU, and are distributed to the other terminals.
    Type: Grant
    Filed: July 9, 1993
    Date of Patent: November 4, 1997
    Assignee: Fujitsu Limited
    Inventors: Yuichi Terui, Toshiaki Usui
  • Patent number: 5231492
    Abstract: A system is disclosed for multiplexing, transmitting, and receiving picture data and sound data, wherein the picture data and sound data are balanced in a limited transmission capacity so as to obtain a better overall quality to effectively use the transmission ability of a medium. The content of at least one of the picture data and sound data are detected and used for control of the content of the transmission. The content of the transmission is controlled by changing data and sound to correct a difference between the processing speed of the picture data and the sound data, thereby improving the quality of a video conference system or the like where the transmission capacity is insufficient.
    Type: Grant
    Filed: November 16, 1990
    Date of Patent: July 27, 1993
    Assignee: Fujitsu Limited
    Inventors: Ryoichi Dangi, Takehiko Fujiyama, Toshiaki Usui, Takashi Kawabata
  • Patent number: 5079548
    Abstract: A data packing circuit, used in a variable length coder, for receiving code words including variable length codes and code length information of the variable length codes, and packing the variable length codes with no gaps into successive units of bits having predetermined length. The code word is shifted in a first direction by a number of bits equal to a shift number, and in parallel, the code word is shifted in a second direction opposite to the first direction by a number of bits equal to the difference between the predetermined length and the shift number, and zero is filled in each vacant bit which is generated by the above shift operations. The shift number is determined by accumulation of the code lengths by modulo-n addition, n being equal to the predetermined number, and a carry addition of the code lengths whether or not a carry occurs over the above predetermined length in the accumulated value.
    Type: Grant
    Filed: September 19, 1990
    Date of Patent: January 7, 1992
    Assignee: Fujitsu Limited
    Inventors: Takehiko Fujiyama, Toshiaki Usui, Ryouichi Dangi, Takashi Kawabata