Abstract: An endoscope processor includes a processor that can be connected to an endoscope including a moving mechanism of a focusing lens included in an objective optical system and an image pickup apparatus. The processor is configured to determine whether or not a transition has been made from a screening state to a proximity state based on positional information of the focusing lens and an image in a proximity determination mode when a variation in an image height in an effective image range with control of the moving mechanism is 1% or less, and when it is determined that a transition has been made to the proximity state, the processor is configured to end the proximity determination mode and control the moving mechanism in an autofocus mode.

Abstract: The subject matter of this specification can be implemented in, among other things, a method of decoding video data that includes decoding compressed input video data using a first entropy coding technique to obtain first decoded data. The method further includes re-encoding the first decoded data using a second entropy coding technique that is different from the first entropy coding technique to obtain re-encoded data. The method further includes storing the re-encoded data in a storage device. The method further includes decoding the re-encoded data using the second entropy coding technique to obtain second decoded data.

Abstract: A program conversion program, a program conversion apparatus and a program conversion method that conversions a program having different process according to the content of an argument into a program which facilitate the analysis are provided.

Abstract: The subject matter of this specification can be implemented in, among other things, a method of decoding video data that includes decoding compressed input video data using a first entropy coding technique to obtain first decoded data. The method further includes re-encoding the first decoded data using a second entropy coding technique that is different from the first entropy coding technique to obtain re-encoded data. The method further includes storing the re-encoded data in a storage device. The method further includes decoding the re-encoded data using the second entropy coding technique to obtain second decoded data.

Abstract: Techniques for optimizing the Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream decoding are disclosed. In one configuration, a device has a first processing circuit operative to decode a Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream into an intermediate signal having a CABAC decoded standard format and a decoded order. A second processing circuit decodes the intermediate signal using a non-CABAC decoding standard. A buffer is provided between the first and second processing circuits to improve processing speeds.

Abstract: Techniques for optimizing the Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream decoding are disclosed. In one configuration, a device has a first processing circuit operative to decode a Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream into an intermediate signal having a CABAC decoded standard format and a decoded order. A second processing circuit decodes the intermediate signal using a non-CABAC decoding standard. A buffer is provided between the first and second processing circuits to improve processing speeds.

Abstract: The present invention provides a program analysis program, a program analysis device, and a program analysis method which can analyze programs and obtain input/output information of the programs effectively.

Abstract: A program conversion program, a program conversion apparatus and a program conversion method that conversions a program having different process according to the content of an argument into a program which facilitate the analysis are provided.

Abstract: In a similar source-code extracting apparatus, a comparison-source source-code fragment specifying unit accepts specification of a source-code fragment that is specified as a reference for comparison, a comparison-target source-code specifying unit accepts specification of a source code group and extracts a source-code fragment similar to the source-code fragment from the source code group, and a result output unit outputs the result of extraction. A comparison-target source-code fragment extracting unit extracts the source code to be compared for similarity with the comparison-source source-code fragment from the source code group, by referring to a syntax tree created from the comparison-source source-code fragment and a syntax tree created from the source code group.

Abstract: A decoder is disclosed that provides dynamic pipelining of an incoming compressed bitstream. The decoder includes decoding logic modules capable of decoding an incoming compressed bitstream, and memory storing logic in communication with at least one of the decoding modules. Preferably, the memory storing logic is capable of determining whether a memory operation is complete that stores the uncompressed video data to memory. In addition, the decoder includes halting logic in communication with the decoding logic and the memory storing logic. The halting logic halts the decoding of the incoming bitstream during a specific time period, which includes a time period wherein the memory operation is incomplete. Finally, initiating logic is included in the decoder that is in communication with the decoding logic and the memory storing logic. The initiating logic of the decoder restarts the decoding when the memory operation is complete.

Abstract: A decoder for decoding a compressed incoming interruptible bitstream is disclosed. The decoder includes an input register that is capable of receiving a latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. The decoder also includes decoding logic, such as variable length decoding logic, or run-length decoding logic, in communication with the input register. Further included in the decoder is an output register in communication with decoding logic, that is also capable of receiving the latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. Finally, the decoder includes a register controller in communication with both the input register and the output register. The register controller is capable of receiving a halt command from the system and, upon receiving the halt command, the register controller sends the latch command to both the input register and the output register.

Abstract: A specification generating method for a computer program comprises the steps of: analyzing the syntax of a predetermined computer program; generating a control flowchart based on the analyzed syntax; generating an intermediate expression table based on the control flowchart; providing block numbers for calls and branched destinations; attaching an item number and a heading to every call and branched destination; and generating the specification of the computer program, using a natural language based on the item number and the heading.

Abstract: A relevant-information retrieval system manages a model which describes a relevancy among a plurality of databases in accordance with associative values or a tree structure. Besides, when the retrieval system has received a search request for a certain database from a searcher, it specifies one of the databases administering information relevant to the certain database, in accordance with the model, and it presents information of the specified database to the searcher.

Abstract: An interleaved all-pass section for a lattice wave digital filter, comprises a first input carrying an interleaved signal, a first adder/multiplier network (AMN) connected to said first input, a second adder/multiplier network (AMN), and a delay element connected between said first AMN and said second AMN, wherein said delay element causes the propagation of signals from said first AMN to said second AMN to be delayed sufficiently to enable said second AMN and said first AMN to process separate signals in parallel.

Abstract: A plurality of disc players are arranged in a vertical direction, a plurality of frames each holding a tray are mounted in a magazine pack. A magazine pack loading means is provided for moving the magazine pack taken into an apparatus body, and a frame separation and holding means is provided for separating the frames one at a time and positions them at predetermined locations corresponding to the disc players when moving the magazine pack by the magazine pack loading means. A tray transfer means is provided for transferring the trays between the predetermined locations and the disc players.

Abstract: The syntax of an input program is analyzed, variables substituted for the substitution sentences from an interim expression thereof are classified into categories by utilizing rules of naming variables or the data structure, and a set of substitution sentences having variables of the same kind substituted for the destinations is picked up and is converted into a table. The syntax is analyzed to obtain a syntax structure and data attribute, and the data flow is analyzed to obtain data flow information. By using such information, the use of the temporary variables in the program is judged and the temporary variables that can be erased are erased. The table conversion and the interim expression from which the temporary variables are erased are replaced by the description of a natural language to form specifications.

Abstract: A circuit for calculating a sum of absolute errors for use in full block search matching in a motion estimation processor is disclosed herein, the circuit being easily implemented and capable of running at 54 Mhz. The circuit accesses search window and reference data from memory and loads the data into rows of laterally interacting processing elements having an architecture capable of fast data processing. A sum of absolute errors between all elements of each row of search data and all elements of each row of reference data is calculated, and the absolute error for all rows of processing elements is totalled. From this total sum of absolute error, the motion vector may be predicted for the next frame.

Abstract: An nth degree function computing device having a low-cost, small scale circuit in which no multipliers are present and which allows high-speed computing operations. The nth degree function computing device comprises two series operators 32 and 38 connected in series, with an adder 44 inserted between them, and with an adder 48 inserted between the output terminal of the second-stage series operator 38 and device output terminal 46. A constant 2a.sub.2 is sent from constant generator 50 to the first input terminal of an adder 34 of the first-stage series operator 32. A constant (a.sub.1 -a.sub.2) is sent from constant generator 52 to first input terminal of adder 44. A constant a.sub.0 is sent from constant generator 54 to the first input terminal of adder 48. With respect to variable x (integer), a clock circuit 56 sends (x+1) synchronized clock pulses CLK.sub.i and x clock pulses CLK.sub.k to registers 36 and 42 of first-stage and second-stage series operators 32 and 38, respectively.

Abstract: A digital filter, in which the operation time can be kept short even when the order of the filter is high. The digital filter comprises a first transversal filter TF.sub.1 which has an input terminal connected to a signal input terminal 10, first delay means DR.sub.1 which has an input terminal connected to the output terminal of first transversal filter TF.sub.1, a second transversal filter TF.sub.2 connected to the output terminal of the first delay means DR.sub.1, second delay means DR.sub.2 which has an input terminal connected to the output terminal of the second transversal filter TF.sub.2, adder AD which has one of the input terminals connected to the output terminal of the second delay means DR.sub.2, third delay means DR.sub.3 which has an input terminal connected to the output terminal of the adder AD and an output terminal connected to the signal output terminal, and a third transversal filter TF.sub.

Abstract: A tri-state driver circuit is disclosed which provides rail-to-rail output swings and does not consume a significant amount of d.c. power.